International Business Machines Corporation

Steve Ostrander

Charles Leon Arvin

Mark William Kapfhammer

Thomas Weiss

Jon Alfred Casey

Thomas Edward Lombardi

Shidong Li

Lawrence Alfred Clevenger

Michael J Ellsworth, Jr

Michael A Gaynes

Arvind Kumar

Mark Kenneth Hoffmeyer

Joshua M Rubin

Kamal Kumar Sikka

Prabjit Singh

Sushumna Iruvanti

Thomas Anthony Wassick

Phillip Duane Isaacs

Frank Louis Pompeo

Brian Richard Sundlof

Richard Francis Indyk

Rajneesh Kumar

Dinesh Gupta

Jason R Eagle

Christopher Michael Marroquin

Bhupender Singh

Maryse Cournoyer

Valérie Anne Oberson

Daren Simmons

Krishna R Tunga

Brian W Quinlan

Catherine Dufort

Kevin Drummond

Stephanie Allard

Moisture-driven degradation of a crack stop in a semiconductor die is mitigated by forming a groove in an upper surface of the die between an edge of the die and the crack stop; entirely filling the groove with a moisture barrier material; preventing moisture penetration of the semiconductor die by presence of the moisture barrier material; and dissipating mechanical stress in the moisture barrier material without presenting a stress riser in the bulk portion of the die. The moisture barrier material is at least one of moisture-absorbing, moisture adsorbing, and hydrophobic.

Mitigating moisture-driven degradation of features designed to prevent structural failure of semiconductor wafers

A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.

Spacer for die-to-die communication in an integrated circuit and method for fabricating the same

A fixture to facilitate fabrication of a heat sink includes a base plate to support a lower section of the heat sink, and multiple registration pins extending from the base plate. A platen is provided over a heat transfer element (HTE) of the heat sink, with the platen including slip fit regions to slip fit around respective registration pins, and with the lower section and HTE disposed between the base plate and the platen, and forming a fixture stack segment aligned with an active region of the cold plate. A load plate is provided which includes slip fit regions configured to slip fit around corresponding registration pins with the load plate disposed over the fixture stack segment. The load plate includes a single load pin centrally disposed to apply a load to the fixture stack segment and facilitate bonding the lower section and HTE together.

Fixture facilitating heat sink fabrication

Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

Direct bonded heterogeneous integration packaging structures

A structure with controlled capillary coverage is provided and includes a substrate including one or more first contacts, a component and adhesive. The component includes one or more second contacts and a rib disposed at a distance from each of the one or more second contacts. The component is disposed such that the one or more second contacts are communicative with the one or more first contacts and corresponding surfaces of the substrate and the rib face each other at a controlled gap height to define a fill-space. The adhesive is dispensed at a discrete point whereby the adhesive is drawn to fill the fill-space by capillary action.

Structure with controlled capillary coverage

Spacer for die-to-die communication in an integrated circuit

Multiple integrated circuit (IC) devices are connected to a top side metallization surface of a multi IC device carrier. The carrier includes resin based substrate layers and associated wiring line layers. To reduce stain of the resin layers, especially in region(s) within the carrier between the IC devices, a stiffener or stiffeners are applied to the back side metallization (BSM) surface of the IC device carrier. The stiffener(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the resin layer(s), thereby mitigating the risk for cracks forming and expanding within the resin layers.

Mitigating cracking within integrated circuit (IC) device carrier

A multiple chip carrier assembly including a carrier having a first surface and a second surface is attached to a plurality of chips is described. The plurality of chips include a first chip and a second chip. Each of the chips has first surface with a first set of solder balls for connecting to a package and a second set of solder balls for connecting to a high signal density bridge element. A second surface of each chip is bonded to the first surface of the carrier. A package has a first surface which is connected to the first sets of solder balls of the first and second chips. A high signal density bridge element having high signal density wiring on one or more layers is connected to the second sets of solder balls of the first and second chips. The bridge element is disposed between the first surface of the package and the first surfaces of the first and second chips.

Multiple chip carrier for bridge assembly

Place a first semiconductor chip onto an alignment carrier with protrusions of the semiconductor chip inserted into corresponding cavities of the alignment carrier, so that the protrusions and cavities locate the semiconductor chip with interconnect contacts overlying a window that is formed through the alignment carrier. Place a second semiconductor chip onto the alignment carrier with protrusions of the second semiconductor chip inserted into cavities of the alignment carrier, so that the protrusions and cavities locate the second semiconductor chip with interconnect contacts of the second semiconductor chip adjacent to the interconnect contacts of the first semiconductor chip and overlying the window. Fasten the semiconductor chips to the alignment carrier. Touch contacts of a interconnect bridge against the interconnect contacts of the first and second semiconductor chips by putting the interconnect bridge through the window.

Precision alignment of multi-chip high density interconnects

A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.

Underfill method and chip package

Growing community of inventors

Poughkeepsie, NY, United States of America

Steve Ostrander