Micron Technology Incorporated

Aptina Imaging Corporation

Steve Oliver

Kyle K Kirby

Warren M Farnworth

Rick C Lake

Salman Akram

Alan G Wood

David R Hembree

James M Wark

William Mark Hiatt

Swarnal Borthakur

Jacques Duparre

Sidney B Rigg

Dave Pratt

Mark Hiatt

Scott Donald Churchwell

Andy Perkins

Shashikant Hegde

Jeff Viens

Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors. Electrically conductive material in contact openings may be electrically connected to the at least one of transistors and capacitors and extend to a back side surface of the semiconductor substrate. Laterally extending conductive elements may extend over the back side surface of the semiconductor substrate and may be electrically connected to the conductive material in the contact openings. At least one laterally extending conductive element may be electrically connected to a first transistor or capacitor and may extend laterally underneath a second, different transistor or capacitor to which the laterally extending conductive element is not electrically connected.

Semiconductor devices including back-side integrated circuitry

A method and apparatus providing a lens master device and use of the same to form a lens template and/or a lens structure. The method includes obtaining a plurality of individual lens masters, each of which has a shaped portion defining at least a portion of a lens structure to be formed. The lens masters are affixed onto a supporting structure to form a lens master device.

Lens master devices, lens structures, imaging devices, and methods and apparatuses of making the same

Present embodiments relate to a semiconductor device having a backside redistribution layer and a method for forming such a layer. Specifically, one embodiment includes providing a substrate comprising a via formed therein. The substrate has a front side and a backside. The embodiment may further include forming a trench on the backside of the substrate, disposing an insulating material in the trench, and forming a trace over the insulating material in the trench.

Semiconductor device having backside redistribution layers and method for fabricating the same

Method and apparatus providing a wafer level fabrication of imager modules in which a permanent carrier protects imager devices on an imager wafer and is used to support a lens wafer.

Method and apparatus providing an imager module with a permanent carrier

Methods for fabricating semiconductor devices, such as complementary metal-oxide-semiconductor (CMOS) imagers, include fabricating transistors and other low-elevation features on an active surface of a fabrication substrate, and fabricating contact plugs, conductive lines, external contacts, and other higher-elevation features on the back side of the fabrication substrate. Semiconductor devices with transistors on the active surface and contact plugs that extend through the substrate are also disclosed, as are electronic devices including such semiconductor devices.

Semiconductor device fabrication methods

The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated.

Semiconductor substrates comprising through substrate interconnects that are visible on the substrate backside

Semiconductor device having backside redistribution layers

Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.

Methods for fabricating and filling conductive vias and conductive vias so formed

Methods for fabricating photoimagers, such as complementary metal-oxide-semiconductor (CMOS) imagers, include fabricating image sensing elements, transistors, and other low-elevation features on an active surface of a fabrication substrate, and fabricating contact plugs, conductive lines, external contacts, and other higher-elevation features on the back side of the fabrication substrate. Imagers with image sensing elements and transistors on the active surface and contact plugs that extend through the substrate are also disclosed, as are electronic devices including such imagers.

Imagers with contact plugs extending through the substrates thereof and imager fabrication methods

Methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices

Method for fabricating semiconductor device having backside redistribution layers

Accurate lens substrates on a waferscale are obtained by forming a polymer material on a lens surface formed on a lens wafer. The substrate may also be thinned by the glass lens surface forming process at the portion of the lens. The polymer material may have the same or different optical properties (refractive index and dispersion) as the lens wafer.

Over-molded glass lenses and method of forming the same

Methods of forming a lens master wafer having aspheric lens shapes. In one embodiment, a substrate is coated with a polymer material. Isolated sections are formed in the polymer material. The isolated sections are reflowed. The reflowed sections are formed into aspheric lens shapes using a lens stamp.

Growing community of inventors

Boise, ID, United States of America

Steve Oliver