Siliconsystems, Inc.

Steve Levy

Dave Hedberg

Chris Cole

Oscar Agazzi

Paul Hurst

Jeremy Tzeng

The present invention utilizes a decision feedback equalizer (DFE)/finite impulse response filter. A plurality of taps of the equalizer supply coefficients to the input function and are updated in a feedback loop. An additional DC tap is provided, with a constant value as its input source. Within reasonable limits, the constant term (i.e. D.C.) in an analog input signal is subtracted out by the action of the constant value DC tap. The coefficients are updated by a decision feedback means such that phase, amplitude and DC offset may all be corrected. In the preferred embodiment, the filter is a T/2 spaced filter in which two samples per baud are utilized by the filter. The filter outputs a complex word which is coupled to a quantizer. The actual constellation locations are compared to the ideal locations in a difference block so that offset errors may be detected. The difference signal is used to update the coefficient values. One of the coefficients so generated is the DC tap in the filter. The product of the modified tap value and the constant input term is combined with the convolutional sum of the input signal to remove constant terms resulting from DC offset in the input signal.

Method and apparatus for analog D.C. offset cancellation

The jitter tracker of the present invention uses a decision-directed error signal as an input to a feedback loop. The error signal is filtered and coupled to a phase locked loop centered at the center of the jitter tracking frequency range, which in the preferred embodiment is 55 Hz. The frequency width and center track and lock frequencies are set by a loop filter. A second order loop is used to acquire the frequency and phase jitter within an acceptable range. Once within this range, a first order loop is used to lock the amplitude to the input signal. The amplitude and phase values are subtracted from the incoming signal so that a new error may be calculated. In the preferred embodiment, the jitter tracker of the present invention is implemented in a digital signal processor. The jitter tracker of the preferred embodiment of the present invention comprises two filter loops. The first loop is used to generate the magnitude of the jitter error. The second loop generates the phase of the jitter error. The input to the jitter tracker is the quadrature portion of a normalized error term. This quadrature portion is multiplied by the cosine of the output of the error loops to generate the magnitude of the error signal. This term is multiplied by a scaling factor and is then integrated to generate a magnitude error term. The quadrature portion of the normalized error signal is multiplied in the second loop by the sine of the loop output. This phase error signal is coupled to a first order filter within a range in the preferred embodiment of plus or minus 10 Hz from a 55 Hz nominal frequency. The output of this first filter is multiplied by nominal 55 Hz vector and integrated to produce a phase error output. The real portion of this phase error signal is generated and combined with the magnitude error to produce a jitter correction factor for use in the receive channel circuitry.

Phase jitter tracker

The present invention is a method and apparatus for implementing a two stage AGC circuit. In the preferred embodiment, the present invention is used as part of a receive channel in a modem. The first stage of the AGC is a 'coarse' AGC and is used to track large signal transients of an input signal. The coarse AGC locks on to transient signals without excessive settling time. In operation, the coarse AGC acquires a new signal by using a nonlinear clipped feedback loop technique supported by a linearized feedback loop. The coarse AGC stage uses an error signal derived from the noncoherent power fluctuations of the incoming signal. The second stage of the AGC circuit is a 'fine' AGC using a decision-directed coherent amplitude error signal and a quick linear feedback loop to correct for finer signal level fluctuations. The fine AGC has a high pass characteristic which decouples its response from that of the equalizer for stability reasons. The present invention avoids performance and response limitations of prior art AGC's in that the coarse stage is not required to have wide band response and associated noisy tracking response. Further, when the input signal is in quadrature amplitude modulation (QAM) the coarse stage tracks by using a nonlinear power detection algorithm which removes the effect of data power modulation. The fine AGC stage utilizes a decision-directed (coherent) error signal and a linear feedback loop with zero excess delay so that wideband response can be achieved without introducing amplitude modulation error in the signal path. As a result, the two stage scheme of the present invention can track rapid gain changes and restore correct data detection within a few baud, limiting error corruption to only one data block.

Method and apparatus for two stage automatic gain control

The present invention employs a four sample per baud timing recovery scheme to achieve fast acquistion of initial timing phase uncertainity and reliable fast tracking with low jitter for non-equalized QAM wave forms. The present invention operates for data timing frequency uncertainties up to 0.02 percent in the preferred embodiment. The timing recovery system is implemented with programmable digital signal processor code in connection with a programmable phase baud timer. The baud timer may be implemented in software or hardware. The present scheme is based on a pair of quadrature (T/4 spaced) timing error signals derived by a wave difference method. In the wave difference method, the envelope power of each baud sample is computed by square summing the real and imaginary samples of the received analog signal.

Digital fast recovery timing algorithm

The present invention is directed to a digital non-coherent pattern detection scheme in which spectral analysis of phase encoded signals is utilized to provide pattern recognition. The present invention is relatively insensitive to the power level of incoming signals. Since the power level is easily detected and determined, the present invention allows the various algorithms to operate quickly. Further, utilizing the magnitude samples of the incoming signal result in a pattern detection scheme that is independent of modulation technique. The present invention utilizes the concept of spectral analysis to determine spectral lines which are present in phase encoded signals. A phase encoded signal such as a DPSK or QAM having an implicit pattern contained therein, which results in unique spectral lines. By detecting the spectral lines in certain combinations, the phase encoded pattern being sent may be identified. For example, 'unscrambled mark', 'S1', and other patterns may be identified using the method of the present invention. In operation, a plurality of receive channels are implemented to detect energy levels at specific frequencies and thereby identify spectral lines. The input signal is demodulated with one of a plurality of modulating frequencies F.sub.0 -F.sub.n in each receive channel, chosen to translate the input spectra signal to baseband. The demodulated signal is low pass filtered and the filtered output is squared, generating a power signal. In the preferred embodiment, the power signal is filtered again to obtain a stochastic average. This averaged signal is coupled to an energy detect block. If energy at the desired spectra is present and of sufficient magnitude, a digital 'one' is provided as output, if sufficient energy is detected, a digital 'zero' is provided as output. A logical 'one' is provided at the output representing the specific pattern detected as indicated by the digital word.

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Nevada City, CA, United States of America

Steve Levy