Wayne Fueling Systems LLC

Advanced Micro Devices Corporation

Dell USA L P

Steve L Belt

Henry Fieglein

Scott R Negley, Iii

John Joseph Morris

Andy Lambrecht

Thomas Cerovski

Drew Jon Dutton

Joseph A Bailey

John C Pate

Matthew Norris

Greg Hudgins

Various exemplary outdoor payment terminals and methods of using outdoor payment terminals are provided. In general, data signals can be transmitted between a payment terminal configured to receive payment information from a customer and a point of sale (POS) configured to authorize the customer's payment and provide various commands, e.g., instructions, to the payment terminal. A payment terminal can include a translator configured to translate commands transmitted from the POS to the payment terminal so the payment terminal carries out the type of command requested by the POS but executes in a way that accounts for payment terminal functionality unknown to the POS.

Outdoor payment terminals

Methods, systems, and devices for secure payment and providing multimedia at fuel dispensers are provided. In general, a fuel dispenser can include a terminal configured to receive secure information and to show multimedia. The terminal can be configured to switch between a first mode and a second mode. The terminal can include a touchscreen. In the first mode, the touchscreen can have a shield enabled thereon that is configured to reduce a field of view of the touchscreen such that the touchscreen is only visible from specific angle(s). In the second mode, the shield can be disabled such that the touchscreen does not have a reduced field of view.

Methods, systems, and devices for secure payment and providing multimedia at fuel dispensers

Fuel dispensers, systems and methods are provided for electronically transmitting data characterizing fueling transactions in a fueling environment, and in particular from a fuel dispenser. In an exemplary embodiment, a fuel dispenser is provided having a printer module that can perform operations that enable any one or more of replacing a printer, providing a user with a printed transaction record at a remote location, and/or provide the user with an electronic transaction record. The application of the printer module can facilitate providing a user with a printed and/or electronic transaction record, while minimizing, or eliminating, changes to standard communication protocol associated with components of a payment terminal that can deliver formatted transaction data to a typical printer. Minimizing or eliminating changes to standard communication protocol associated with providing users with transaction records can facilitate retrofitting the printer module to existing fuel dispensers, and/or simplify design considerations for new dispenser.

Fuel dispenser printer module

Printerless fuel dispenser

An automatic IR port detection device is provided in a portable computer including a first and a second transceiver data port. An external device is adjacent the computer and includes at least one external transceiver data port. An IR port detection and scanning program in the computer is actuated by an initiating key combination. A controller in the computer generates a systems management interrupt in response to the initiating key combination being actuated. An IR scan timer is initiated in response to the systems management interrupt being generated. A system BIOS in the computer actuates the first transceiver data port to scan for an external IR signal and sequentially actuates the second transceiver data port to scan for the external IR signal in response to the absence of the external IR signal received by the first transceiver data port. The IR scan timer is resettable in the absence of the IR signal being received from the external transceiver data port by either of the first and second transceiver data ports.

Automatic IR port detection and switching

A computer system having distributed compression and decompression logic for compressed data movement within the computer system. This provides increased efficiency and reduced bus bandwidth requirements. The computer system includes various standard components, including a CPU, chip set logic, main memory, one or more expansion buses, and various peripheral devices coupled to the expansion buses. Various devices may be connected to the PCI bus, including graphics accelerator hardware, audio logic, a hard drive, and a network interface card, and other multimedia devices, as desired. In the preferred embodiment, the bridge logic and/or memory controller, one or more of the multimedia devices, the hard drive, and the network interface controller each includes compression/decompression (codec) logic which performs compression and decompression operations. Thus, when a device desires to perform a transfer on the bus, the codec in the device preferably compresses the data before transferring the data onto the bus. The receiving or destination device includes codec logic which receives the compressed data and decompresses the data, and the decompressed data is then used or stored by the device. Thus, the majority of data transfers on the bus are compressed data transfers, i.e., comprise transfers of compressed data. This optimizes or reduces the required bus transfer bandwidth.

Computer system having distributed compression and decompression logic

A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Thus multimedia devices such as video cards, audio cards, etc., as well as communications devices, transfer real-time data through a separate bus without requiring arbitration for the PCI bus. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems. In various embodiments, multimedia devices transmit addressing and control information for a multimedia bus transfer either over the PCI bus or using a separate serial control channel. The multimedia bus may also comprise separate multimedia channels for different data types. In various embodiments, methods transfer periodic multimedia data over the multimedia bus.

Computer system including a multimedia bus which utilizes a separate

A computer system including a plurality of multimedia devices each having a high-speed memory data channel for accessing system memory. Each multimedia device has a high speed link directly to system memory, which is preferably single or multiple ported memory. These individual links are preferably high speed serial interconnects but, alternatively, may be 4-bit, 8-bit, 16-bit, 24-bit, 32-bit, 64-bit or any combination thereof. In this embodiment, intelligent buffering is preferably implemented within the core logic, and arbitration for access to main memory is preferably implemented within the core logic. Each of the multimedia devices uses its dedicated memory data channel to perform data accesses and transfers directly to the main memory, bypassing PCI bus arbitration and PCI bus cycles. Alternatively, each of the multimedia devices includes a high speed memory channel directly to the memory controller in the core logic for accessing system memory. The computer system is thus optimized for real-time applications and provides increased performance over current computer architectures.

Computer system including a plurality of multimedia devices each having

An integrated processor includes CPU core, cache memory, and cache controller coupled to a local bus via a local bus interface. The integrated processor further includes memory controller for coupling system memory to the local bus, and a bus interface unit for coupling external peripheral devices to the local bus. The cache controller includes an address tag and state logic circuit which keeps track of a physical address in system memory which corresponds to each entry within cache memory. Address tag and state logic circuit contains state information that indicates whether each cache line is valid and/or dirty. The cache controller includes a snoop control circuit which monitors the local bus to determine whether a memory cycle has been executed by an alternate bus master. During such a memory cycle of an alternate bus master, a comparator circuit determines whether a cache hit has occurred. If a cache read hit occurs with respect to a dirty cache line, the cache controller asserts an inhibit signal which causes the memory controller to ignore the cycle. The read request is instead serviced by the cache controller by providing the requested data from the cache memory to local bus 112. If a cache write operation occurs, data is written into the system memory via system memory controller, and the data is concurrently latched into the corresponding line of the cache memory. The status of cache line may further be updated to clean if the data transfer encompassed a complete cache line.

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Pflugerville, TX, United States of America

Steve L Belt