Nexflash Technologies, Inc.

Unity Semiconductor Corporation

Steve K Hsia

Kyung Joon Han

Dung Tran

Joo Weon Park

Jong Seuk Lee

Gyu-Wan Kwon

Darrell Rinerson

Steven W Longcor

Makoto Nagashima

Dae Hyun Kim

Larry Matheny

A memory fabrication apparatus includes a pair of targets arranged so as to be spaced apart from one another within a closed vacuum vessel, each target of said pair of targets having a sputtering surface facing the sputtering surface of the other target of said pair of targets; and substrate holder adapted to receive facing target sputtering a CMO material on an electrode.

Low temperature deposition of complex metal oxides (CMO) memory materials for non-volatile memory integrated circuits

An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n&#x2212; source region. A heavily doped p+ region known as a 'halo' is disposed in the channel adjacent the heavily doped n+ drain. The floating gate is spaced away from the channel region by a generally thin tunnel oxide. A lightly doped source with a graded source/channel junction reduces source side CHE generation. In one variation, a thicker oxide between the source and the floating gate reduces CHE injection from the source side. A heavily doped drain with a halo implant in the channel adjacent the drain enhances drain side CHE generation.

Virtual ground single transistor memory cell, memory array incorporating same, and method of operation thereof

A memory array contains memory cells designed to be erased using Fowler-Nordheim (&ldquo;FN&rdquo;) tunneling through the channel area, and programmed using either channel hot electron injection (&ldquo;CHE&rdquo;) or channel-initiated secondary electron injection (&ldquo;CISEI&rdquo;). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.

Method and apparatus for multiple byte or page mode programming of a flash memory array

A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.

Threshold voltage convergence

Growing community of inventors

San Jose, CA, United States of America

Steve K Hsia