Qualcomm Incorporated

Unisys Corporation

Steve Joseph Bezuk

Lizabeth Ann Keser

Reynante Tamunan Alvarado

Hong Bok We

Jerry Ihor Tustaniwskyj

Nicholas Ian Buchan

Jianwen Xu

Damion B Gastelum

William Michael Stone

Gene Hyde McAllister

Christine Sung-An Hau-Riege

Jon Gregory Aday

Tushar R Gheewala

Nicholas Ka Ming Yu

Kevin Patrick Caffey

Robert E Rackerby

Maria D Alvarez

Patrick A Weber

Robert J Baseman

Stephen A Campbell

You-Wen Yau

A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold compound. In one example, the package may be a wafer level package that allows an external connection on the backside of the package to enable manufacturing in a panel or wafer form.

Interface substrate and method of making the same

A wafer level package device may include a molding compound that encapsulates a substrate, a back end of line and front end of line layer on the substrate and a passivation layer of a redistribution layer without encapsulating a metal layer on the passivation layer. The molding compound may eliminate sidewall chipping and cracking as well as reduce the need for back side lamination.

Wafer level package without sidewall cracking

Some novel features pertain to an integrated device that includes a substrate, a first die coupled to the substrate, a first encapsulation layer coupled to the substrate and the first die, and a second encapsulation layer in the first encapsulation layer. The second encapsulation layer includes a set of wires configured to operate as vias. In some implementations, the integrated device includes a set of vias in the first encapsulation layer. In some implementations, the integrated device further includes a second die coupled to the substrate. In some implementations, the second encapsulation layer is positioned between the first die and the second die. In some implementations, the integrated device further includes a cavity in the first encapsulation layer, where the second encapsulation layer is positioned in the cavity. In some implementations, the cavity has a wall that is non-vertical. In some implementations, at least one of the wires is non-vertical.

Integrated device comprising wires as vias in an encapsulation layer

Some implementations provide a semiconductor device (e.g., die) that includes a substrate, several metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the plurality of metal layers, a first metal redistribution layer coupled to the pad, and a second metal redistribution layer coupled to the first metal redistribution layer. The second metal redistribution layer includes a cobalt tungsten phosphorous material. In some implementations, the first metal redistribution layer is a copper layer. In some implementations, the semiconductor device further includes a first underbump metallization (UBM) layer and a second underbump metallization (UBM) layer.

Stacked redistribution layers on die

A method of stretching solder joints between the input/output pads of an electrical component and corresponding input/output pads on a substrate includes the steps of: melting the solder joints; confining the component while the solder joints are melted such that the component can only move substantially perpendicular to the substrate; pulling the component, while the component is confined, by an external force in a direction away from the substrate to thereby stretch the melted solder joints; compelling the movement of the component to stop when the component has moved a predetermined distance; and, solidifying the solder joints while the component is compelled to stop. By stretching the solder joints with the above method, the solder joint shape can be changed from convex to concave; and thermally induced stress/strain in the joint is substantially reduced.

Method of stretching solder joints

Enhanced density of electrical and/or mechanical interconnections between adjacent wafers within integrated circuit assemblies and structural integrity of those interconnections under temperature cycling conditions, is attained by utilizing laser assisted chemical vapor deposition to fabricate precisely configured metal posts which serve as such interconnections.

Interconnect for layered integrated circuit assembly

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Poway, CA, United States of America

Steve Joseph Bezuk