Silicon Graphics, Incorporated

Steve J Ciavaglia

Peter Y Hsu

Joseph T Scanlon

William A Huffman

John Brennan

Joseph P Bratt

Paul Kingsley Rodman

Man K Tang

A method for preventing deadlock due to the need for data exclusivity when performing forced atomic instructions in a multi-level cache in a multi-processor system. The system determines whether an aligned multi-byte word in which the data of a forced atomic instruction, such as an integer store operation, is exclusive in a first level cache. If so, the forced atomic instruction is allowed to enter a second level cache pipeline. If not, the forced atomic instruction is prevented from entering the second level cache pipeline and a cache miss and fill operation is initiated to cause the aligned word to be exclusive in the first level cache.

Method for preventing multi-level cache system deadlock in a

A set associative translation lookaside buffer (TLB) that supports variable sized pages without requiring the use of a separate block TLB. The TLB includes a hashing circuit that creates an index into the TLB for a virtual address using different bits from the virtual address depending on the page size of the address, and a comparator that compares virtual address identifiers or portions of virtual address identifiers stored in the TLB to the current virtual address to determine if a translation to the current virtual address is stored in the TLB.

Variable page size translation lookaside buffer

A split level cache memory system for a data processor includes a single chip integer unit, an army processor such as a floating point unit, an external main memory and a split level cache. The split level cache includes an on-chip, fast local cache with low latency for use by the integer unit for loads and stores of integer and address data and an off-chip, pipelined global cache for storing arrays of data such as floating point data for use by the array processor and integer and address data for refilling the local cache. Coherence between the local cache and global cache is maintained by writing through to the global cache during integer stores. Local cache words are invalidated when data is written to the global cache during an army processor store.

Memory system including local and global caches for storing floating

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Williston, VT, United States of America

Steve J Ciavaglia