Intel Corporation

Steve Hunt

Peter D MacWilliams

Gurbir Singh

Dan Wheeler Patterson

Bindi A Prasad

Phil G Lee

A computer system having a processor-cache protocol supporting multiple cache configurations is described. The computer system has a processor having a cache control circuit to control multiple cache memory circuits. The processor including its cache control circuit is coupled to a cache bus. A second level cache memory is also coupled to the cache bus. The cache control circuit controls the second level cache by issuing commands that are executed by the second level cache.

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Felton, CA, United States of America

Steve Hunt