Advanced Micro Devices Corporation

Steve Horne

Gopi Ganapathy

Robert C Thaden

A test circuit and test technique for scan testing integrated circuits is disclosed. The test circuit includes a drive 1 or drive 0 scan element which utilizes fewer transistors than conventional scan latches. The testing technique utilizes the clock input to the latches in the ICs for propagating data through the latches. The test circuit and test techniques may be used with microprocessors and particularly RISC microprocessors. The test technique includes coupling a drive 1 or drive 0 element to a logic element coupled to a general latch. The drive 1 or drive 0 scan element allows the general latch to be clocked by a clock signal such as a .phi.1 clock signal or .phi.2 clock signal.

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Austin, TX, United States of America

Steve Horne