Apple Inc.

Qualcomm Incorporated

Other

Mediatek Singapore Pte. Ltd.

Steve Hengchen Hsu

Raheel Khan

Mohanned Omar Sinnokrot

Thirunathan Sutharsan

On Wa Yeung

Dan MingLun Chuang

Hadi Afshar

Gayatri Singaravelu

Chia-An Lin

Hsiao-Han Ma

Wei-Lun Hung

A cellular modem processor can include dedicated processing engines that implement specific, complex data processing operations. The processing engines can be arranged in pipelines, with different processing engines executing different steps in a sequence of operations. Flow control or data synchronization between pipeline stages can be provided using a hybrid of firmware-based flow control and hardware-based data dependency management. Firmware instructions can define data flow by reference to a virtual address space associated with pipeline buffers. A hardware interlock controller within the pipeline can track and enforce the data dependencies for the pipeline.

Systems and methods for synchronizing data processing in a cellular modem

A polar decoder circuit can execute successive cancellation list polar decoding on multiple threads concurrently. An LLR update engine of the polar decoder circuit and a sort engine of the polar decoder circuit can operate concurrently, with the LLR update engine computing updated path metrics for one codeword while the sort engine sorts candidates for one or more other codewords according to path metrics already computed by the LLR update engine. Threads corresponding to different codewords can cycle sequentially between the LLR update engine and the sort engine.

Systems and methods for multithreaded successive cancellation list polar decoding

A cellular modem processor can include dedicated processing engines that implement specific, complex data processing operations. To implement PDCCH decoding, a cellular modem can include a pipeline having multiple processing engines, with the processing engines including functional units that execute instructions corresponding to different stages in the PDCCH decoding process. Flow control and data synchronization between instructions can be provided using a hybrid of firmware-based flow control and hardware-based data dependency management.

Instruction-based multi-thread multi-mode PDCCH decoder for cellular data device

A device protects data dependency for memory access. The device includes a memory and a processor. The processor executes memory access instructions including load instructions and store instructions. The processor includes load circuitry to execute the load instructions; and store circuitry to execute the store instructions. Each memory access instruction includes a token index field containing a token index that associates the memory access instruction with a memory location. The processor further includes dispatch circuitry to dispatch instructions to the load circuitry and the store circuitry; and a token registry to record used token indices according to token index fields in the memory access instructions dispatched by the dispatch circuitry.

Token-based data dependency protection for memory access

Systems and methods for performing a rake-finger operation on a vector processor are described herein. In one embodiment, a method for rake-finger processing comprises loading samples from a register into an execution unit, performing a rake-finger operation on the samples in the execution unit, and writing results from the rake-finger operation to the register. Performing the rake-finger operation comprises performing a finite impulse response (FIR) filter operation, and performing a despread operation, wherein filtered samples from the FIR filter operation are input to the despread operation without going through the register.

Instruction and method for fused rake-finger operation on a vector processor

Methods and apparatus are described for interference cancellation of interference components of a time domain signal in the frequency domain. A communications device receives a time domain sequence and generates overlapping time domain segments from the time domain sequence. The overlapping time domain segments are then converted to the frequency domain to generate frequency domain representations of the overlapping time domain segments. The frequency domain representations are stored in a residual memory, and interference components are directly removed from the frequency domain representations stored in the residual memory in the frequency domain.

Frequency domain interference cancellation and equalization for downlink cellular systems

Methods and apparatus are described for interference cancellation of interference components of a time domain signal in the frequency domain. A time domain sequence is received, and a plurality of overlapping time domain segments is generated from the time domain sequence. Frequency offset compensation to compensate for frequency offset associated with a serving cell is performed in the time domain, and the overlapping time domain segments are then converted to the frequency domain. Additional frequency offset compensation may be performed to compensation for the frequency offset associated with interfering cells.

Intercell frequency offset compensation for frequency domain interference cancellation and equalization for downlink cellular systems

A method and apparatus for digitizing color images on photographic and other media insures accurate registration between color planes and provides a digitization capability substantially equivalent to the dynamic range of photographic film.

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San Diego, CA, United States of America

Steve Hengchen Hsu