Nvidia Technology UK Limited

Icera, Inc.

Nvidia Corporation

Steve Felix

Steve Allpress

Abdellatif Bellaouar

Carlo Luschi

Abdelkader Medles

Hamid Safiri

Pete Cumming

Method and receiver for processing a signal in a wireless communication system in which the signal comprises a sequence of chips. The signal is receive data at least one rake finger and sampled. There is a time spacing tbetween successive samples less than the time spacing tbetween successive chips in the signal. Channel conditions on the channel are estimated and based on estimated channel conditions by the following steps: monitoring timing of the signal on one of the at least one rake finger to determine a time difference between the timing of the signal on the one of the at least one rake finger and the timing of the generation of the samples, the determined time difference being a multiple of t, where t&#x3c;t; aligning the timing of the generation of the samples with the timing of the signal on the one of the at least one rake finger to within a timing range t.

Method and system for processing a signal

Method and computing system for controlling a supply voltage in the computing system. A voltage related indication for use in setting the supply voltage of the computing system is stored, and a supply voltage is set for the computing system based on the stored voltage related indication. A crash of the computing system is detected, and in dependence thereon, an adjusted indication is determined for use in the computing system. An adjusted supply voltage is set based on the adjusted indication, and the adjusted indication is stored for further use of the computing system.

Method and system for controlling a supply voltage

A method, device and computer program product is provided for sending a data signal and a clock signal between a radio frequency circuit of a device and a baseband circuit of the device, the radio frequency circuit being configured for at least one of transmission and reception of radio signals in a radio frequency band, where the clock signal has a clock frequency F. The method comprises selecting the clock frequency Fto be a rational multiple of the 0.270833 MHz symbol rate of the Global System for Mobile Communications (GSM) standard and a rational multiple of the 3.84 MHz chipping rate of the Wideband Code Division Multiple Access (WCDMA) interface. The clock frequency Fis selected such that the clock signal can be generated using a 38.4 MHz or 19.2 MHz reference clock signal, a non-fractional Phase Locked Loop clock multiplier and an output divider, without first having to divide down the reference clock signal. The data signal and the clock signal can then be sent between the radio frequency circuit and the baseband circuit using the selected clock frequency F.

Method and device for sending signals between a radio frequency circuit and a baseband circuit

A method of sending a data signal and a clock signal between a radio frequency circuit of a device and a baseband circuit of the device. The method comprises: determining whether at least one of the data signal and the clock signal is disturbing in that it has a harmonic within the radio frequency band. If it is determined that at least one of the data signal and the clock signal is disturbing, the method further comprises: scrambling the at least one disturbing signal to flatten the spectrum thereof for frequencies below the clock frequency F, setting a respective at least one indicator to indicate that the at least one disturbing signal has been scrambled, and sending the at least one scrambled signal between the radio frequency circuit and the baseband circuit. The method further comprises, subsequent to the step of sending the at least one scrambled signal, descrambling the at least one scrambled signal if the respective at least one indicator is set.

Integrated circuit and method for generating a clock signal, the integrated circuit comprising (i) a frequency locked loop comprising a voltage controlled oscillator configured to receive a control input and to generate a clock signal determined by the control input; and (ii) a microprocessor configured to be powered by a supply voltage and to receive the clock signal generated by the voltage controlled oscillator. The integrated circuit is configured to use the supply voltage as the control input, such that the clock signal is determined by the supply voltage.

Digital frequency locked loop

Method, circuitry and device for spreading a clock signal in which the clock signal is received at an input of a variable delay line, the clock signal having been generated by a clock signal generator. In one embodiment, for each edge of the clock signal, the delay introduced by the variable delay line is set in accordance with a stored delay value. For each of a plurality of consecutive edges of the clock signal, the stored delay value is either incremented or decremented based on a randomly generated value for that edge. A spread version of the clock signal is output from the variable delay line, wherein each edge of the spread version of the clock signal is delayed by the respective delay that is set for that edge of the clock signal.

Spreading a clock signal

According to an embodiment of the invention, a method and system is disclosed for determining log-likelihood ratios for a coded set of individual bits () of a quadrature amplitude modulation (QAM) codeword. In the method at most two constant values () may be determined to perform a set of predetermined functions, the output of each of function is based on the constant values and at least one received component corresponding to the codeword, to determine log-likelihood ratios () for each individual bit of the set of individual bits of the codeword. The QAM codeword may correspond to at least a portion of a signal of a wireless device, such as a mobile third-generation device operating according to a Wideband Code-Division Multiple Access (WCDMA) standard.

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Bristol, United Kingdom

Steve Felix