International Business Machines Corporation

Steve Esser

Dharmendra S Modha

John Vernon Arthur

Myron Dale Flickner

Andrew S Cassidy

Jun Sawada

Pallab Datta

Rathinakumar Appuswamy

Filipp Akopyan

A neural inference chip includes a global weight memory; a neural core; and a network connecting the global weight memory to the at least one neural core. The neural core comprises a local weight memory. The local weight memory comprises a plurality of memory banks. Each of the plurality of memory banks is uniquely addressable by at least one index. The neural inference chip is adapted to store in the global weight memory a compressed weight block comprising at least one compressed weight matrix. The neural inference chip is adapted to transmit the compressed weight block from the global weight memory to the core via the network. The core is adapted to decode the at least one compressed weight matrix into a decoded weight matrix and store the decoded weight matrix in its local weight memory. The at core is adapted to apply the decoded weight matrix to a plurality of input activations to produce a plurality of output activations.

Compressed weight distribution in networks of neural processors

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San Jose, CA, United States of America

Steve Esser