Silicon Storage Technology, Inc.

Steve Choi

Hung Quoc Nguyen

Loc Bao Hoang

Hieu Van Tran

Thuan Vu

Anh Ly

Sang Thanh Nguyen

Sheng-Hsiung Hsueh

Alexander Kotov

A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

Flash memory array system including a top gate memory cell

Systems and methods are disclosed including memory cells arranged in sectors. In one exemplary implementation, each memory cell may include a top gate, a source, a top gate line coupling memory cells in a sector, and a word line coupling memory cells together. Moreover, the top gate line may be dynamically coupled to the word line. Other exemplary implementations may relate to drivers for driving the word line and/or top gate line, multilevel memory cell, and/or floating gate line features.

Flash memory array with a top gate line dynamically coupled to a word line

Flash memory array having control/decode circuitry for disabling top gates of defective memory cells

Method for handling a defective top gate of a source-side injection flash memory array

A circuit to screen for defects in an addressable line in a non-volatile memory array comprises a current mirror circuit which has a plurality of mirroring stages. The current mirror circuit is connected to the addressable line and receives a control signal and mirrors the control signal to provide a current to the addressable line. In a preferred embodiment, the current mirror circuit provides a high voltage current to the addressable line which is used to effectuate an operation such as program or erase to the memory cells connected to the addressable line. The change in state or the absence of change in state of the memory cells connected to the addressable line can be used to screen for defects in the addressable line.

Circuit and a method to screen for defects in an addressable line in a non-volatile memory

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Irvine, CA, United States of America

Steve Choi