Sandisk Technologies Inc.

Sandisk Corporation

Steve Chi

Ekram Bhuiyan

Henry H Yuan

Daniel P Nguyen

Po-Shen Lai

Yongliang Wang

Vincent Anthony Condito

A storage system and method for dynamic duty cycle correction are disclosed. In one embodiment, a controller of a storage system provides a clock signal to the memory, receives the clock signal back from the memory, monitors the duty cycle of the clock signal received back from the memory, and in response to the duty cycle of the clock signal received back from the memory not meeting a target value, adjusts the duty cycle of the clock signal provided to the memory so that the duty cycle of the clock signal received back from the memory better meets the target value. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Storage system and method for dynamic duty cycle correction

An apparatus may include detection circuitry configured to detect a presence of a host clock signal on a host clock line, and detect a level of a host supply voltage upon detection of the host clock signal. The detection circuitry may configure a core regulator in a regulation mode or in a bypass mode based on the detected level of the host supply voltage. Additionally, components of analog circuitry of a non-volatile memory system may be partitioned into different supply voltage domains, with those components active during a sleep state receiving one supply voltage and those components inactive during the sleep state receiving a different supply voltage.

Voltage level detection and analog circuit arrangements for memory systems

A switching rectifier circuit includes a pulse width modulation controller, a voltage switching circuit, a pulse width modulation comparator, an error amplifier, a voltage reference, a high threshold voltage comparator and a low threshold voltage comparator. A varying output voltage of the voltage regulator is sampled and compared to a high threshold voltage reference and a low threshold voltage reference. When the sampled output voltage is equal to or greater than the high threshold voltage reference the output voltage is decreased. When the sampled output voltage is equal to or less than the low threshold voltage reference the output voltage is increased.

Fast response pulse width modulation control for switching regulator

A host power-on reset control circuit includes a comparator connected to receive both a divided version of a supply voltage and a reference voltage. The comparator generates and outputs a high digital state signal when the divided version of the supply voltage is at least as large as the reference voltage. The control circuit includes an output node connected to transmit a power-on reset control signal. The control circuit includes pulldown circuitry connected between the comparator output and the output node. The pulldown circuitry maintains the output node at a reset voltage level as the supply voltage rises to a host operational level, based on a signal present at the comparator output. The control circuit includes pullup circuitry connected between the supply voltage and the output node. The pullup circuitry maintains the output node at a non-reset voltage level after the supply voltage has risen to the host operational level.

Apparatus and method for host power-on reset control

A data storage device includes a non-volatile memory and a host interface. A method includes supplying a first supply voltage to the host interface during a first mode of operation of the non-volatile memory. The method further includes supplying a second supply voltage to the host interface in response to a transition from the first mode of operation to a second mode of operation of the non-volatile memory.

Host interface of a memory device supplied with regulated or non-regulated power based on operating mode of the memory device

A data storage device includes a signal source. A load is responsive to the signal source. A method includes adjusting an impedance of the load to reduce an impedance mismatch between the signal source and the load.

Load impedance adjustment for an interface of a data storage device

A system and method of providing an analog make before break circuit includes a first transistor coupled in series with a second transistor, the first transistor being configured for conducting a high portion of an input signal, the second transistor being configured for conducting a low portion of the input signal. A third transistor is configured to interrupt a connection between the input signal and a first transistor input node, the third transistor having a third transistor threshold voltage between of about 90 and about 110 percent of a second transistor threshold voltage. A fourth transistor is configured to interrupt a connection between the input signal and a second transistor input node, the fourth transistor having a fourth transistor threshold voltage of between about 90 and about 110 percent of a first transistor threshold voltage.

Analog break before make system, method and apparatus

A soft-start generation system is configured to generate a soft-start voltage. The soft-start generation system includes sawtooth circuitry configured to generate current having a sawtooth waveform and staircase circuitry configured to generate current having an ascending staircase waveform. A ramp-up current may be generated that is a combination of the sawtooth current and the staircase current. The ramp-up current may continuously ramp up to a predetermined current level. The soft-start voltage may be generated based on the ramp-up current.

Digital soft start with continuous ramp-up

Techniques and circuits are described by which analog circuits may be quickly driven to desired states at startup in a fast and accurate manner.

Analog circuit configured for fast, accurate startup

Delay circuits are described for which the delay remains substantially constant within a desired range of variation of supply voltage and/or temperature.

Accurate low-power delay circuit

An electronic product includes an application specific semiconductor chip (ASIC) device which includes in its circuitry both a linear regulator module configured to be coupled to an optional external capacitance and a capless regulator module configured to be coupled to internal capacitance of the electronic product. Control logic of the ASIC device is responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device. The control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation.

Multi-regulator power delivery system for ASIC cores

A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

Self-configurable multi-regulator ASIC core power delivery

Methods and systems for automatically and/or locally adjusting power-valid detection. In one class of embodiments, local power-on-reset circuits are included in individual power islands; in another class of embodiments, the power-on-reset circuit is automatically reprogrammed, depending on the detected interface voltage level, to use the same circuitry for power-valid detection in either case.

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Cupertino, CA, United States of America

Steve Chi