Bay Microsystems, Inc.

Steve C Chen

Man Dieu Trinh

Simon S Chong

Goichiro Ono

Charles F Gershman

Barry T Lee

Jun-Wen Tsong

Tony J Chiang

Ryzsard Bleszynski

Eric K Yang

Martin Chang

Ray Chen

A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service ('QoS'). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port.

Network processor architecture

A technique for managing traffic within a network processor integrated circuit (IC) involves establishing multiple queue groups, associating a different hardware counter with each queue group, and then using the hardware counters to support rate shaping and scheduling of all of the queues in the queue groups. For example, 512 queue groups of thirty-two queues each queue group are established for a total of 16,384 (16 k) different queues and a different hardware counter is associated with each queue group for a total of 512 hardware counters. The group-specific hardware counters are used to implement hardware-based rate shaping and scheduling of all 16 k queues in a resource efficient manner that supports high throughput, e.g., on the order of 40 Gbps.

Highly-scalable hardware-based traffic management within a network processor integrated circuit

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Cupertino, CA, United States of America

Steve C Chen