Advanced Micro Devices Corporation

Steve Avanzino

Minh Van Ngo

Fei Wang

Lu You

Christy Mei-Chu Woo

Robert A Huertas

Connie Pin-Chin Wang

Christine Hau-Riege

The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved and hillock formation is significantly reduced by sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a plasma containing NH and N , ramping up the introduction of trimethylsilane and then initiating deposition of a silicon carbide capping layer. Embodiments include treating the exposed surface of in-laid Cu with a soft NH plasma diluted with N , shutting off the power, discontinuing the N flow and introducing He, then ramping up the introduction of trimethylsilane in three stages, and then initiating plasma enhanced chemical vapor deposition of a silicon carbide capping layer, while maintaining substantially the same temperature of 335&deg; C. throughout plasma treatment and silicon carbide capping layer deposition. Embodiments also include forming Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than 3.9.

Method of forming SiC capped copper interconnects with reduced hillock formation and improved electromigration resistance

A method of forming interconnects on a semiconductor chip is disclosed which comprises the steps of: depositing a barrier layer and a copper seed layer on the semiconductor chip; depositing on the copper seed layer an enhancement layer; annealing the semiconductor chip a first time after the copper seed layer and the enhancement layer are deposited to form an annealed layer; electroplating a copper layer on the semiconductor chip; and annealing the semiconductor chip a second time after the copper layer is deposited on the annealed layer to form an annealed copper conductive layer.

Utilization of annealing enhanced or repaired seed layer to improve copper interconnect reliability

A process for manufacturing a semiconductor device includes forming a first metallization level, forming a first etch stop layer, forming a low-k dielectric layer, forming a cap layer, depositing a resist, forming an opening; removing the resist, curing the dielectric material, etching the first etch stop layer, and filing the opening with metal. The first etch stop layer is formed over the first metallization level, and the low-k dielectric layer material is formed over the first etch stop layer. The cap layer is formed over the low-k dielectric layer material, and the resist is formed over the dielectric layer. Etching is used to form the opening. The resist is removed with an O stripping process. Curing of the dielectric material forms a dielectric layer and occurs after the resist is removed.

Method for preventing damage of low-k dielectrics during patterning

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Cupertino, CA, United States of America

Steve Avanzino