Intel Corporation

Steve A Peterson

Chee How Lim

Songmin Kim

Usman Mughal

Razi Uddin

Raghu P Raman

A system supports Double Date Rate (DDR) or Single Data Rate (SDR) data transfers on a data bus between a processor and a memory device. A controller-side interface block connects to a memory-side interface block for generating the control signals and transferring stored data from the memory device to the processor.

Double data rate memory interface

In a system, such as an open-drain bus architecture system, a termination impedance can be dynamically coupled or de-coupled from a bus. The termination impedance is coupled to the bus by a dynamic control circuit if a signal is being received from the bus or if a binary 1 is driven on the bus. The termination impedance is de-coupled from the bus by the dynamic control circuit if a binary 0 is driven on the bus. Coupling the termination impedance to the bus improves signal quality by providing a matching impedance. De-coupling the termination impedance reduces power dissipation and improves receiver noise margin.

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Sacramento, CA, United States of America

Steve A Peterson