Mstar Semiconductor, Inc.

Sterling Smith

Henry Tin-Hang Yung

Jiunn-Kuang Chen

Chia-Ming Yang

Ke-Chiang Huang

Ta-Chan Kao

Chun-Chia Chen

Guo-Kiang Hung

Steve Wiyi Yang

Hsian-Feng Liu

Chih-Tien Chang

Horng-Der Chang

Huimin Tsai

Sheng-Yao Liu

Song-Yi Lin

Chung-Ching Chen

Her-Ming Jong

Eer-Wen Tyan

Ming-Chieh Yeh

Chao-Ping Huang

Wen Cai Lu

Kuo-Feng Hsu

Chih-Shiun Lu

Yo-Lin Chen

Hung-Kun Chen

Chung-Ho Ning

Chi-Kang Liu

Cheng-Yu Lu

Wen-Cai Lu

Yong-Wang Liu

Hsu-Lin FanChiang

Po Nien Lin

Ying-Jia Zhu

Jianqiu Chen

Jian-Ping Cheng

Jianping Cheng

Ellen Chen Yeh

A reference voltage generation circuit includes an auto-activation unit, an operational amplifier unit, and a tail current resistor. An input of the operational amplifier is grounded via the tail current resistor. The auto-activation unit is coupled to the operational amplifier so that the circuit operates at an operating point. A reduction of current noises, circuit area, and overall cost occurs implemented through the described tail current unit

Reference voltage generation circuit

A method for implementing a touch screen on a display panel and associated apparatus is provided. Cross locations of source lines and gate lines of the display panel are arranged for sensing a user touch control. In a sensing phase for sensing touch control, capacitance changes due to the touch control are sensed via the source lines. In a display phase, driving electricity is transmitted via the source lines for driving the display panel to display.

Method for implementing touch screen on display panel and associated apparatus

An apparatus and method for adjusting the pixel resolution of an input image is disclosed. According to the present invention, the pixel resolution of the input image is adjusted by oversampling an analog signal representative of the input image at a higher frequency than the pixel rate of the original image, then digitally downscaling to the desired horizontal resolution of an output image. The horizontally downscaled image is then stored in a buffer memory and subsequently scaled up to the desired vertical resolution of the output image. Preferably, oversampling of the analog signal is performed at a frequency that is an integer multiple of the input pixel rate, thus providing coherent sampling to help avoid aliasing artifacts in the sampled image.

Apparatus and method for increasing pixel resolution of image using coherent sampling

A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.

Apparatus and method of generating universal memory I/O

A dual phase-locked loop (PLL) circuit includes a phase/frequency detector, a charge pump, a frequency tuning circuit and an N divider. The frequency tuning circuit includes a coarse-tuning circuit, for coarse-tuning an output frequency of the dual PLL circuit to approximate a target frequency; a fine-tuning circuit, for fine-tuning the output frequency of the dual PLL circuit to the target frequency; and a current control oscillator (CCO), for generating an output signal of the dual PLL circuit. The output frequency of the output signal is equal to the target frequency.

Dual phase-locked loop circuit and method for controlling the same

A flat panel display device, LCD controller and associated method is provided. The flat panel display device includes a display panel, a lamp for providing a backlight source for the display panel, a power transformation module for providing a power source for the lamp, a non-volatile storage unit for storing program code, and a display controller. The display controller includes an image processing module for processing image data and outputting processed results to the display panel, and a digital pulse width modulation module for adjusting on and off time of the power transformation module according to a synchronization signal.

Flat panel display device, controller, and method for displaying images

A receiver includes an adaptive equalizer, a power detecting unit and an adjusting unit. The adaptive equalizer is for receiving a signal and generating an equalized signal. The power detecting unit, coupled to the adaptive equalizer, is for detecting the strength of the equalized signal during a first period to generate a first strength signal, and detecting the strength of the equalized signal during a second period to generate a second strength signal. The adjusting unit, coupled to the power detecting unit and the adaptive equalizer, is for adjusting the compensation strength for the adaptive equalizer according to the first and second strength signals.

Receiver and method for adjusting adaptive equalizer of receiver

A flat panel display device, LCD controller and associated method is provided. The flat panel display device includes a display panel, a lamp for providing a backlight source for the display panel, a power transformation module for providing a power source for the lamp, a non-volatile storage unit for storing program code, and a display controller. The display controller includes an image processing module for processing image data and outputting processed results to the display panel, and a digital pulse width modulation module for adjusting on and off time of the power transformation module with reference to a synchronization signal.

A delay locked loop includes a pulse generator, a delay unit, a phase detector and a control unit. The pulse generator generates a pulse signal and a determination signal according to an input clock signal. The delay unit delays the pulse signal according to a digital control signal to generate a delayed pulse signal. The phase detector detects a time delay of the delayed pulse signal according to the determination signal to generate a detection result. The control unit generates a digital control signal according to the detection result to control the delayed pulse signal by a delay amount.

Delay locked loop and associated method

A phase generating apparatus generates an output clock having a desired phase according to a digital signal. The apparatus includes a phase selecting unit and a phase generating unit. The phase selecting unit selects one of a plurality of input clocks according to a portion of bits of the digital signal to generate a reference clock. Each of the input clocks respectively has a difference phase. The phase selecting unit divides the frequency of the reference clock, and selectively delays the frequency-divided reference clock according to another portion of bits of the digital signal to generate the output clock.

Phase generating apparatus and method thereof

A Sigma-Delta modulator with a shared operational amplifier (op-amp) includes an integrated circuit, having two integrators sharing the op-amp, capable of integrating two input signals of the two integrators; a plurality of quantizers, coupled to the integrating circuit, for comparing outputting signals of the integrators with a predetermined signal and then generating digital outputting signals; a plurality of DACs, respectively coupled to the quantizers, for converting the digital outputting signals to analog feedback signals to the integrators; and a clock generator, for providing clock signals to the integrating circuit and the quantizers. Accordingly, layout area and power consumption of the modulator are reduced due to the shared op-amp.

Sigma-delta modulator with shared operational amplifier and associated method

An AV switching method capable of auto-configuring a plurality of AV input signals and associated apparatus is provided. An audio-video detector capable of auto-configuring the AV input signals includes an audio-video detecting module, an impedance adjustment module, and an audio-video switching module. The audio-video detecting module receives and detects the AV input signals to generate an AV detecting result. The impedance adjustment module adjusts matching impedance for the AV input signals according to the AV detecting result. The audio-video switching module switches the AV input signals to output AV output signals according to the AV detecting result.

Method of auto-configuring audio-video signals and associated apparatus

A read state retention circuit and method are disclosed. The read state retention circuit comprises a charge storage unit, charging unit, sensing circuit and state indicator. The charging circuit is coupled to the charge storage unit for charging the charge storage unit. The sensing circuit is coupled to the charge storage unit for sensing a voltage level of the charge storage unit. The state indicator is coupled to the sensing circuit for outputting an indication signal in response to the voltage level.

Read state retention circuit and method

The invention discloses a finite impulse response (FIR) filter for processing a digital input signal to generate a digital output signal. The FIR filter has a tap amount N and a decimation ratio D. The FIR filter includes a first memory, a multiplier, and an accumulation module. For each input sample of the digital input signal, the first memory provides N/D corresponding tap coefficients from a plurality of tap coefficients in turn. The multiplier multiplies the input sample with the N/D corresponding tap coefficients in turn to generate N/D product values. The accumulation module adds the N/D product values to N/D previous accumulation values to generate N/D renewed accumulation values respectively. If one of the accumulation values has already accumulated N product values, the accumulation module outputs the accumulation value as an output sample of the digital output signal.

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Hsinchu, Taiwan

Sterling Smith