Microsoft Technology Licensing, LLC

Stephen Z Au

John Allen Tardif

Nhon Toai Quach

Michael G Love

Harjit Singh

Tracy Sharpe

Gregory George Williams

Eiko Junus

Thomas Zou

One disclosed computing system comprises a x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP) that is connected to the PCIe RC through a PCIe link, the PCIe EP being connected to an AMBA&#xae; bus. The interconnect chip may communicate with the IO device via the AMBA&#xae; bus in an AMBA&#xae; compliant manner and communicate with the host system in a PCIe compliant manner. This communication may include receiving a command from the processor, sending the command to the IO device over the AMBA&#xae; bus, receiving a response from the IO device over the AMBA&#xae; bus, and sending over the AMBA&#xae; bus and the PCIe link one or more DMA operations to the memory. Further communication may include sending an IOAPIC interrupt to the processor of the host system according to PCIe ordering rules.

Support for IOAPIC interrupts in AMBA-based devices

A Multiple Input Shift Register (MISR) is used to generate signatures, based on data from a device under test, in order to validate the proper sequence and content of the data over a defined period of time. The MISR described herein includes the ability to 'tag' the signatures for each time period using an incrementing value, and make that tag and the signature readable by a test controller. The MISR has the flexibility to be reset to a known initial state (or otherwise load a seed value) at the beginning of each time period or to continue accumulating signatures without being reset (or using the seed value). Accumulation of signatures over an extended period of time allows a test controller to validate that no errors occurred during a long term test without having to closely monitor the intermediate results.

Digital signature generation for hardware functional test

A memory controller is utilized to overcome NAND flash memory's propensity for comprising bad blocks of memory. The memory controller utilizes minimal hardware and is essentially transparent to a device requesting access to the NAND memory. A NAND flash memory device is configured to comprise a set of main blocks of memory and a set of auxiliary blocks of memory. Each block is divided into pages of memory and each page includes metadata. The metadata includes a block status indicator, indicating whether a block is good or bad. When receiving a request to access a page in the NAND flash memory, if the block in which the page resides is good, that block is accessed. If the block is bad, auxiliary memory is searched until a block containing the address of the bad block in its metadata is found. The found block is accessed in lieu of the bad block.

NAND flash memory management

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Stephen Z Au