International Business Machines Corporation

Stephen Wu

Chandrasekharan Kothandaraman

William Vincent Huott

Adam J McPadden

Uma Srinivasan

Dan Moy

Brian W Messenger

William Joseph Ferrante

John Cassels

Peter Wang

Edwin Soler

Gabriel Chiulli

Effendi Leobandung

Yunsheng Song

Xu Ouyang

Rao H Desineni

Hargurpreet Singh

According to a first aspect of the present invention, there is provided a method, a computer system and a computer program product. The method, computer system and computer program product including measuring an initial state of a set of SRAM bits on the wafer, identifying a first set of signature SRAM bits on the wafer, of the set of SRAM bits on the wafer, where the first set of SRAM bits comprise a consistent initial state greater than a first threshold percentage of times, measuring physically dimensions of features of the first set of SRAM bits on the wafer; and identifying a set of signature SRAM bits of the first set of SRAM bits on the wafer, wherein the set of signature SRAM bits comprise physical dimensions of features which correlate to the initial state of each correlated SRAM bit.

Mask fingerprint using mask sensitive circuit

Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a 'zero' state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the 'zero' state bit and selective transistor biasing, skews the 'zero' state bit towards the complementary &#x201c;one&#x201d; state bit. This induces an increase voltage thresholds of the identified SRAM cells.

SRAM margin recovery during burn-in

Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a 'zero' state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the 'zero' state bit and selective transistor biasing, skews the &#x201c;zero&#x201d; state bit towards the complementary &#x201c;one&#x201d; state bit. This induces an increase voltage thresholds of the identified SRAM cells.

An apparatus and method for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.

Apparatus and method for programming an electronically programmable semiconductor fuse

A design structure for an apparatus for programming an electronically programmable semiconductor fuse. The apparatus applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.

Structure of an apparatus for programming an electronically programmable semiconductor fuse

A method for identifying potentially defective integrated circuit chips and excluding them from future testing as wafers move through a manufacturing line The method includes data-collecting steps, tagging the chips on wafers identified as potentially bad chips based on information collected as the wafer moves down the fabrication line, evaluating test cost savings by eliminating any further tests on the tagged chips preferably using a test cost database. Considering all the future tests to be preformed, the tagged chips are skipped if it is determined that the test cost saving is significant. Tagging bad chips is based on various criteria and models which are dynamically adjusted by performing the wafer final test on samples of the tagged chips and feeding-back the final test results. The dynamic adaptive adjustment method preferably includes a feedback loop or iterative process to evaluate financial tradeoffs when assessing the profit of salvaging chips against the additional test costs.

Method of adaptively selecting chips for reducing in-line testing in a semiconductor manufacturing line

The present disclosure is directed to numerical test data reporting using an image file and subsequent analysis of the test data. A method for capturing and analyzing test data in accordance with an embodiment includes: capturing multi-bit integer values of test data; writing each multi-bit integer value to a multi-bit vertical field in an image file; extracting the multi-bit integer values from the multi-bit vertical fields in the image file; and analyzing the extracted multi-bit integer values.

Numerical test data reporting in an image file and subsequent analysis

Reporting and/or analyzing test data from a plurality of tests of an array structure using a data array. One method includes obtaining the test data, and reporting the test data in a data array, which includes at least two portions representing different tests. Data stored in the data array is organized according to a translation table, which describes the locations of data for tests and criteria for data to be analyzed within the data array. Numerous other data arrangements such as a coordinate file listing a pre-defined maximum number of fail points, or a chip report including fail points by chip may also be generated. The data array reports all test data in a more easily generated and stored form, and may be converted to an image. A data analysis method for analyzing data using the data array is also presented.

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Poughkeepsie, NY, United States of America

Stephen Wu