International Business Machines Corporation

Stephen Wesley MacQuarrie

Voya Rista Markovich

Frank Daniel Egitto

David John Russell

Eric A Johnson

Luis Jesus Matienzo

James Warren Wilson

Elizabeth F Foster

David Erle Houser

Raymond Thomas Galasco

Jeffrey Alan Knight

Thomas E Kindl

Stephen John Kosteva

Eric P Dibble

Eric H Laine

Amarjit S Rai

Steven Joel Diffenderfer

Wayne R Storr

Mark L Janecek

William T Wike

Jerzy Maria Zalesinski

Irving Memis

Randall Joseph Stutzman

Scott Preston Moore

An electronic package device is disclosed including a microelectronic package and a heat sink positioned over the microelectronic package. A thermal interface element is positioned between the microelectronic package and the heat sink. The thermal interface element is elongated and has differing thicknesses along its length to enhance the dissipation of heat.

Optimization of electronic package geometry for thermal dissipation

In an integrated circuit package employing solder bump technology, a metal layer placed on the surface of a substrate below an array of bonding pads is split and displaced from its axis at selected locations to preserve electrical continuity, but to also lower the height of an insulating solder mask layer at those locations.

Selective C4 connection in IC packaging

A method and structure for forming a metalized blind via. A dielectric layer is formed on a metallic layer, followed by laser drilling a depression in the dielectric layer such that a carbon film that includes the carbon is formed on a sidewall of the depression. If the laser drilling does not expose the metallic layer, then an anisotropic plasma etching, such as a reactive ion etching (RIE), may be used to clean and expose a surface of the metallic layer. The dielectric layer includes a dielectric material having a carbon based polymeric material, such as a permanent photoresist, a polyimide, and advanced solder mask (ASM). The metallic layer includes a metallic material, such as copper, aluminum, and gold. The carbon film is in conductive contact with the metallic layer, and the carbon film is sufficiently conductive to permit electroplating a continuous layer of metal (e.g., copper) directly on the carbon film without need of an electrolessly plated layer underneath the electroplated layer. The laser drilling is accomplished using a laser radiation having a wavelength between about 180 nanometers and about 600 nanometers. The depression may have any cross-sectional shape and any spatial distribution of depths. As an example, the depression may include a blind via, a rectangular channel, or a combination thereof.

Fabrication of a metalized blind via

A method and structure for forming a metalized blind via. A dielectric layer is formed on a metallic layer, followed by laser drilling a depression in the dielectric layer such that a carbon film that includes the carbon is formed on a sidewall of the depression. If the laser drilling does not expose the metallic layer, then an anisotropic plasma etching, such as a reactive ion etching (RIE), may be used to clean and expose a surface of the metallic layer. The dielectric layer comprises a dielectric material having a carbon based polymeric material, such as a permanent photoresist, a polyimide, and advanced solder mask (ASM). The metallic layer includes a metallic material, such as copper, aluminum, and gold. The carbon film is in conductive contact with the metallic layer, and the carbon film is sufficiently conductive to permit electroplating a continuous layer of metal (e.g., copper) directly on the carbon film without need of an electrolessly plated layer underneath the electroplated layer. The laser drilling is accomplished using a laser radiation having a wavelength between about 180 nanometers and about 600 nanometers. The depression may have any cross-sectional shape and any spatial distribution of depths. As an example, the depression may include a blind via, then the blind via may have any cross-sectional shape, such as circular or non-circular, a rectangular channel, or a combination thereof.

A pinning process including the steps of gold-plating through-holes in a laminate carrier and crimping old or gold-plated pin located in the through-holes to form a pin head on the top and a pin bulge on the bottom of the laminate carrier to produce a plastic pin grid array. A variety of mechanical forming processes may be employed to form the pin heads and pin bulges and cause the pin to at least partially, and preferably substantially, fill and contact the gold-plated through-hole including swage pinning, impact pinning, and double-die pinning operations. By combining the steps of gold-plating through-holes of a laminate carrier and using a mechanical pinning process to crimp a gold or gold-plated pin in the through-holes, a reliable mechanical and electrical connection may be established between the pin and the metal lines both inside and on the surface of the laminate carrier without the need for lead-containing solders and pastes.

Process of producing plastic pin grid array

An apparatus and method attaching a heatsink to a surface of an electronic package comprising a substrate, an integrated circuit chip attached to the surface of the substrate, an encapsulant encapsulating the integrated circuit chip and contacting at least a portion of the surface of the substrate, and an orifice formed in the top portion of the encapsulant to attach the heatsink to the surface of the electronic package. The heatsink may be attached and removed as desired to allow for package identification or rework.

Integral design features for heatsink attach for electronic packages

A printed circuit board is provided comprising a substrate, a conductor on the surface of the substrate, and an electronic component mounted on the conductor. The printed circuit board includes a first thermally conductive layer within the substrate and a second thermally conductive layer on a portion of the surface of the substrate and spaced from the electronic component. The electronic component is thermally coupled to the second thermally conductive layer by a thermally conductive aperture positioned within the substrate and connected to the conductor and the first thermally conductive layer. The first thermally conductive layer is connected to the second thermally conductive layer by a plurality of apertures also positioned in the substrate. Another printed circuit board is also provided comprising a first plurality of laminate dielectric layers, a conductor on a surface of the first plurality of laminated dielectric layers, and an electronic component mounted on the conductor. The printed circuit board includes a second plurality of laminated dielectric layers connected to the first plurality of laminated dielectric layers by a flexible web. The flexible web includes a first thermally conductive layer positioned within the first plurality of dielectric layers. A thermally conductive aperture thermally connects the electronic component to the first thermally conductive layer. A plurality of thermally conductive apertures is positioned within the second plurality of dielectric layers and thermally couples the first thermally conductive layer to a second thermally conductive layer which is included on a portion of a surface of the second plurality of dielectric layers and spaced from the electronic component. The flexible web portion thus allows positioning of the second thermally conductive layer in a plane remote from the electronic component when it is positioned in a confined space.

Enhanced heat-dissipating printed circuit board package

A package for mounting an integrated circuit chip to a circuit board or the like is provided. The package includes a chip carrier which has a metal substrate including first and second opposed faces. A dielectric coating is provided on at least one of the faces, which preferably is less than about 20 microns in thickness, and preferably has a dielectric constant from about 3.5 to about 4.0. Electrical circuitry is disposed on the dielectric coating, said circuitry including chip mounting pads, connection pads and circuit traces connecting the chip mounting pads to the connection pads. An IC chip is mounted by flip chip or wire bonding or adhesive connection on the face of the metal substrate which has the dielectric coating thereon. In any case, the IC chip is electrically connected to the chip mounting pads either by the solder ball or wire bond connections. Electrical leads extend from the connection pads on the chip carrier and are connected to corresponding pads on a circuit board or the like to provide I/O signals for the IC chip. In certain embodiments, additional heat sinks can be attached to the chip carrier and, also in certain embodiments, chips can be mounted on both sides of the chip carrier to increase the capacity of the chip carrier.

Metal substrate having an IC chip and carrier mounting

A semiconductor device package and method includes a thick, integrated circuit chip stack having a substantially planar bottom surface with a plurality of terminals. A carrier substrate is provided, also having a substantially planar surface, and being adapted to mount the chip stack. The substrate has a plurality of terminals and may preferably be made of a metallized ceramic. The terminals of the chip stack are adapted to be connected to the terminals of the substrate. Means are provided for mounting the chip stack on the substrate, as well as means for making electrical connections between the terminals of the chip stack and the terminals of the substrate. Finally, encapsulating means are used for supporting and maintaining the chip stack mounted on the carrier substrate. J leads connect the substrate to a circuit card.

Method of making interconnections between a multi-layer chip stack to a

A pinning process including the steps of gold-plating through-holes in a laminate carrier and crimping a gold or gold-plated pin located in the through-holes to form a pin head on the top and a pin bulge on the bottom of the laminate carrier to produce a plastic pin grid array. A variety of mechanical forming processes may be employed to form the pin heads and pin bulges and cause the pin to at least partially, and preferably substantially, fill and contact the gold-plated through-hole including swage pinning, impact pinning, and double-die pinning operations. By combining the steps of gold-plating through-holes of a laminate carrier and using a mechanical pinning process to crimp a gold or gold-plated pin in the through-holes, a reliable mechanical and electrical connection may be established between the pin and the metal lines both inside and on the surface of the laminate carrier without the need for lead-containing solders and pastes.

Growing community of inventors

Vestal, NY, United States of America

Stephen Wesley MacQuarrie