Texas Instruments Corporation

Stephen Wayne Spriggs

Bryan David Sheffield

George B Jamison

Suresh Balasubramanian

Vikas K Agrawal

Mohan Mishra

Eric L Badi

Brian D Borchers

Suresh Balasuramanian

Methods, apparatus, systems and articles of manufacture are disclosed that improve performance while reading memory. The method includes initializing an output of a of a sensing circuit to be a first logic high value, obtaining, from the memory, a first current corresponding to a memory bit stored in the memory, replicating the first current, determining whether the replicated first current is greater than a second current, and in response to determining that the replicated first current is greater than the second current, generating a second logic high value at the output of the sensing circuit.

Methods and apparatus to improve performance while reading a one-time-programmable memory

Methods, apparatus, systems and articles of manufacture are disclosed to improve performance while reading a one-time programmable memory. An example apparatus includes: a voltage boost circuit including a first output, a second output, a first input configured to be coupled to a controller, a second input coupled to a first output of a decoder, a third input coupled to a second output of the decoder; and a multiplexer including a first input coupled to the first output of the voltage boost circuit, a second input coupled to the second output of the voltage boost circuit, a third input coupled to an array of memory, and an output coupled to a sensing circuit.

Methods and apparatus to improve performance while reading a one-time programmable memory

A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Self-clocking memory device

A method for evaluating an output of a sequential circuitby storing a series of output pulses from the sequential circuitand determining whether the output pulsestoggled as desired. Also a circuitfor evaluating an outputof a sequential circuitthat determines if the output pulsestoggled as desired.

Error bit method and circuitry for oscillation-based characterization

Method of operating a memory at high speed using a cycle ready status output signal

The memory array contains two layers representing word lines of different rows. Each row contains multiple bit cells sharing the same word line. The two layers are stacked one on top of another to form a high density memory array.

High density memory array

An actual sense amplifier senses a signal received on a bit line to generate a bit, and a latch latches the bit at a time point specified by a latch enable signal. A tracking circuit generates the latch enable signal in an appropriate time window. The tracking circuit may contain a dummy sense amplifier implemented similar to the actual sense amplifier and a dummy column from which the actual sense amplifier senses a signal received upon accessing the dummy memory array. The latch enable signal may be generated after the dummy sense amplifier generates a bit representing the sensed signal. The time taken by the dummy sense amplifier to generate the bit depends on the load offered by the dummy memory array. Accordingly, the dummy memory array is designed to offer sufficient load to ensure that the latch enable signal is generated in an appropriate time window.

Tracking circuit enabling quick/accurate retrieval of data stored in a memory array

A sense amplifier which senses whether current is present on a bit line, and generates one logical value if current is present and another logical value if current is not present. As the sense amplifier can be implemented to generate such logical values with a current signal of low strength, memory arrays with correspondingly low drive strength can be implemented. As a result, memory systems which consume minimal power and having high density can be provided. In addition, as the sense amplifiers can operate without any reference signals, the implementation of sense amplifiers may be simplified.

Sense amplifier for a memory array

Cycle ready circuit for self-clocking memory device

A method and circuit for verifying the burst-mode operation and the frequency characterization of a self-timed sequential circuit in burst mode by detecting and measuring an output of the self-timed sequential circuit

Characterization of self-timed sequential circuits

A memory device ( ) includes a memory array ( ) having storage units ( ) arranged in a plurality of rows ( ). A row decoder ( ) receives address information and determines which of the plurality of rows ( ) to enable. According to the determined row ( ), a row selector ( ) drives the storage units ( ) associated with the determined row ( ) to provide their outputs onto respective bitlines ( ) for identification by a bitline sensor ( ). If the received address information indicates an out of range address that does not identify any of the plurality of rows ( ) of the memory array ( ), an out of range decoder ( ) provides such determination to drive an out of range selector ( ) to enable storage units ( ) arranged in a single row ( ) of a bitline driver ( ). Outputs from the storage units ( ) are applied to the respective bitlines ( ) during an out of range address occurrence to prevent the bitlines ( ) from being placed in an undesirable floating state.

Memory device and method for handling out of range addresses

A method of reducing power supply current transients in a memory array caused by a simultaneous change in logic state of numerous CMOS digital circuits during a memory write cycle. Write driver enable signals (ENT, ENC) and bitcell enable signals (WBC1-WBC24) are sequentially delayed in time during the write cycle through use of the propagation delay of inverters (INV1-INV24-7). The sequential time delay reduces the number of circuits that are simultaneously changing logic state at any given time during the write cycle. The power supply current transient is transformed from a single, large change in current to a series of smaller changes displaced in time from each other during the write cycle. The ground bounce of the power supply network attributed to the current transient is significantly reduced, such change in ground potential being directly related to the magnitude of the current transient and its rate of change with respect to time.

Memory device and method of reducing ground bounce in a memory device

The write port circuits of a static memory cell includes a first conditional conduction path between a first output of the latch and ground active if and only if both a word line input and a write data true bit line input receive active signals. The write port circuit includes a second conditional conduction path between a second output of the latch and ground active if and only if both the word line and a write data complement bit line receive active signals. The first and second conditional conduction paths may be formed by a series connection of the source-drain paths of two transistors. In each conditional conduction path the gate of a first transistor receives a corresponding column signal and the gate of a second transistor is connected to the word line. The first and second transistors for each conduction path may be N-channel MOS transistors formed in a single N-type region. The first and second transistors forming the conditional conduction paths may be in either order. The word line transistors may bee shared between bit line transistors of a single memory cell or of memory cells in plural contiguous adjacent columns. The memory cells may include a plurality of write ports with this inventive write port circuit used for each write port.

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Rowlett, TX, United States of America

Stephen Wayne Spriggs