Agere Systems Inc.

Lucent Technologies Inc.

Stephen Ward Downey

Edward Belden Harris

Sailesh Mansinh Merchant

Allen Yen

Paul B Murphey

Thomas Michael Wolf

An inductor formed on a semiconductor substrate, comprising active device regions. The inductor comprises conductive lines formed on a dielectric layer overlying the semiconductor substrate. The conductive lines are patterned and etched into the desired shape, in one embodiment a planar spiral. A region of the substrate below the inductor are removed to lower the inductive Q factor.

Method of forming a spiral inductor in a semiconductor substrate

The present invention provides a capacitor for use in a semiconductor device having a damascene interconnect structure, such as a dual damascene interconnect, formed over a substrate of a semiconductor wafer. In one particularly advantageous embodiment, the capacitor, comprises a first capacitor electrode, such as copper, comprised of a portion of the damascene interconnect structure, an insulator layer formed on the damascene interconnect structure wherein the insulator layer is a passivation layer, such as silicon nitride. The passivation layer may be an outermost or final passivation layer, or it may be an interlevel passivation layer. The capacitor further includes a second capacitor electrode comprised of a conductive layer, such as aluminum, that is formed on at least a portion of the insulator layer.

Capacitor for integration with copper damascene processes and a method of manufacture therefore

Spiral inductor formed in a semiconductor substrate

The present invention provides a method of manufacturing a semiconductor device. In one embodiment, the method includes forming a positive relief structure from a material located on a substrate, the step of forming the positive relief structure leaving an unwanted remnant of said material proximate a base of the positive relief structure. The method further includes cleaning the positive relief structure. In addition, the method includes removing the unwanted remnant with a gas containing fluorine and that is substantially free of hydrogen.

Method of manufacturing a semiconductor device employing a fluorine-based etch substantially free of hydrogen

A process ( ) for forming a metal interconnect ( ) in a semiconductor device ( ) using a photoresist layer ( ) having a thickness (T) of no more than 0.66 microns without forming a notch in the side ( ) of the interconnect. A reactive ion etching process ( ) used to remove portions of a metal layer ( ) to form the interconnect includes a burst etch step ( ) wherein a first high flow rate ( ) of passivation gas is delivered, followed by a main metal etch step ( ) wherein the flow rate of passivation gas is reduced to a second lower value.

Method for avoiding notching in a semiconductor interconnect during a metal etching step

Capacitor for integration with copper damascene processes

The invention includes a process for the production of semiconductor devices comprising the steps of depositing a metal layer on a semiconductor substrate, depositing a hardmask layer on said metal layer, depositing a photoresist on said hardmask layer, patterning said photoresist, thereby exposing and patterning portions of said hardmask layer, etching said exposed portions of said hardmask layer with a hardmask etchant, thereby exposing and patterning portions of said metal layer, removing, or not, said photoresist, and etching said exposed portions of said metal layer with a metal etchant and semiconductor devices made by said process.

Growing community of inventors

Orlando, FL, United States of America

Stephen Ward Downey