Xilinx, Inc.

Stephen W Trynosky

Trevor J Bauer

Philip Bryn James-Roxby

Prasanna Sundararajan

Eric R Keller

Derek R Curd

Jeffrey V Lindholm

Scott P McMillan

Richard J LeBlanc

Punit S Kalra

Vincent P Eck

Philip B James-roxby

Richard J Leblanc

Scott P Mcmillan

Brandon J Blodget

A programmable logic device, such as a field programmable gate array, is partially reconfigured using a read-modify-write scheme that is controlled by a processor. The partial reconfiguration includes (1) loading a base set of configuration data values into a configuration memory array of the programmable logic device, thereby configuring the programmable logic device; (2) reading a first frame of configuration data values from the configuration memory array; (3) modifying a subset of the configuration data values in the first frame of configuration data values, thereby creating a first modified frame of configuration data values; and (4) overwriting the first frame of configuration data values in the configuration memory array with the first modified frame of configuration data values, thereby partially reconfiguring the programmable logic device. The steps of reading, modifying and overwriting are performed under the control of a processor.

Partial reconfiguration of a programmable logic device using an on-chip processor

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Boulder, CO, United States of America

Stephen W Trynosky