Micron Technology Incorporated

Intel Corporation

Stephen W Russell

Hernan Adolfo Castro

Stephen H Tang

Fabio Pellizzer

Lorenzo Fratin

Max F Hineman

Enrico Varesi

Mark Fischer

Derchang Kau

Gianpaolo Spadini

Paolo Fantini

Jong-Won Sean Lee

Ahmed Nayaz Noemaun

Innocenzo Tortorelli

Andrea Redaelli

H Montgomery Manning

David A Kewley

Swapnil Lengade

Andrea Gotti

David Ross Economy

Brian J Cleereman

Santanu Sarkar

Tony M Lindenberg

Tao D Nguyen

Anthony C Krauth

Rex Stone

David H Wells

Agostino Pirovano

Karthik Sarpatwari

Dale Collins

Anna Maria Conti

Giulio Albini

Sanjay Rangan

Fred Daniel Gealy, Iii

Pengyuan Zheng

Zia Alan Shafi

Luca Laurin

Lequn Jennifer Liu

Davide Fugazza

Durga Prasanna Panda

Kyle Armstrong

Sara Vigano

Alessandro Sebastiani

Michael J Irwin

Yao Jin

HMontgomery Manning

Chandra S Danana

Rekha Chithra Thomas

Yongiun J Hu

Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.

Methods of forming conductive pipes between neighboring features, and integrated assemblies having conductive pipes between neighboring features

Methods, systems, and devices for memory cell formation in three dimensional memory arrays using atomic layer deposition (ALD) are described. The method may include depositing a stack of layers over a substrate and forming multiple piers through the stacks of layers. The method may further include forming multiple cavities through the stacks of layers and forming multiple voids between layers of the stacks of layers. Additionally, the method may include forming multiple word lines based on depositing a conductive material in the voids and forming multiple memory cells based on depositing an active material on an inside surface of the cavities using ALD.

Memory cell formation in three dimensional memory arrays using atomic layer deposition

Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

Memory array decoding and interconnects

Methods, systems, and devices for word line structures for three-dimensional memory arrays are described. A memory device may include word line structures that support accessing memory cells arranged in a three-dimensional level architecture. The word line structures may be arranged above a substrate and be separated from each other by respective dielectric layers. Each word line structure may include word line members and a word line plate that is connected to each word line member. Each word line plate may include a contact that may be coupled with a word line decoder operable to bias the word line plate. To couple the word line plate to the word line decoder, the memory device may include first vias that extend through holes in the word line plates and are coupled with second vias that extend from a respective contact through openings in the word line plates above the contact.

Word line structures for three-dimensional memory arrays

Methods, systems, and devices for sparse piers for three-dimensional memory arrays are described. A semiconductor device, such as a memory die, may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide mechanical support for subsequent processing. For example, a memory die may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. In some examples, the alternating layers may be formed into one or more pairs of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns to provide mechanical support between instances of the cross-sectional patterns, or between layers of the cross-sectional patterns (e.g., when one or more layers are removed from the cross-sectional patterns), or both.

Sparse piers for three-dimensional memory arrays

Methods, systems, and devices for dense piers for three-dimensional memory arrays are described. In some examples, a memory device may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate. For example, a memory device may include alternating layers of a first material and a second material. In some examples, the alternating layers may be formed into a pair of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns, and may provide mechanical support of cross-sectional pattern of the remaining material. In some examples, the piers may further act as a separator between memory cells or other features of the memory device. For example, the piers may extend into at least a portion of the interleaved comb structures, and may accordingly act as barriers during subsequent depositions of materials.

Dense piers for three-dimensional memory arrays

Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

Techniques for forming self-aligned memory structures

Methods, systems, and devices for access line grain modulation in a memory device are described. A memory cell stack in a cross-point memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A barrier material may be formed above the memory cell stack. The barrier material may initially have an undulating top surface. In some cases, the top surface of the barrier material may be planarized. After the top surface of the barrier material is planarized, a metal layer for an access line may be formed on the top surface of the barrier material. Planarizing the top surface of the barrier material may impact the grain size of the metal layer. In some cases, planarizing the top surface of the barrier material may decrease the resistivity of access lines formed from the metal layer and thus increase current delivery throughout the memory device.

Access line grain modulation in a memory device

Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.

Buried lines and related fabrication techniques

Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

Cross-point memory array with access lines

Thin film transistors and related fabrication techniques

Methods, systems, and devices for memory device decoder configurations are described. A memory device may include an array of memory cells and decoder circuits. The array may include one or more memory cells coupled with an access line, and a decoder circuit may be configured to bias the access line to one or more voltages. The decoder circuit may include a first transistor coupled with the access line and a second transistor coupled with the access line. The first transistor may be a planar transistor having a first gate electrode formed on a substrate, and the second transistor may be a trench transistor having a second gate electrode that extends into a cavity of the substrate, where a length of a first gate electrode may be greater than a length of the second gate electrode.

Memory device decoder configurations

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Boise, ID, United States of America

Stephen W Russell