Motorola Corporation

Semiconductor Components Industries, LLC

Cypress Semiconductor Corporation

Freescale Semiconductor,inc.

Stephen W Dow

David F Moeller

Praveen Manapragada

Radhika Venkatasubramanian

Victor Simileysky

Jeffrey C Durec

David K Lovelace

David William Moeller

Prasad Rao Kotra

Brian M Ballweber

Brian Ballweber

Ataur Rehman Khan

Eric C Maass

Bill Marlin

A DC-DC converter and method of operating the same are provided to increase efficiency in window-mode. Generally, the method begins in a coasting-period with receiving in the converter a window-mode enable signal, and opening a switch through which a low reference voltage generator is coupled to a capacitively-charged switched reference (SR) on a first input of a low-side-comparator. Operation of all circuits and devices in the converter, except the comparator is suspended. The voltage on the SR is compared to a feedback voltage (vfb) coupled to a second input of the comparator from a regulated rail coupled to an output of the converter, to sense a change in the voltage on the regulated rail as it is discharged through a load coupled thereto. When vfb is less than the SR voltage, in a burst-period operation of circuits and devices is resumed, and the switch is closed to recharge the SR.

PMU technique for ultra-low leakage

Apparatuses and methods of operating a flexible and optimized power management unit (PMU) for multiple power supply scenarios are described. One integrated circuit includes a first terminal to couple to an unregulated power supply, a second terminal to couple to a regulated power supply, a first regulator, and a second regulator. The first regulator outputs a first supply voltage in a first configuration, and the second regulator outputs a second supply voltage in a second configuration. The first and second regulators do not operate concurrently.

Flexible and optimized power management unit (PMU) for multiple power supply scenarios

In one embodiment, a voltage regulator uses a first current to charge a by-pass capacitor for a first time period and uses a second current after the first time period.

Method of forming a voltage regulator and structure therefor

In one embodiment, a linear regulator is formed with a variable miller compensation circuit that varies a zero of the linear regulator proportionally to a load current supplied by the regulator.

Linear regulator and method therefor

In one embodiment, a programmable voltage regulator stores data representing a programmable configuration of the regulator. The regulator is configured to verify the validity of the stored data before using it to control the operation of the programmable voltage regulator.

Method of forming a programmable voltage regulator and structure therefor

An integrated center frequency selectable resonant coupling network suited for use in an integrated circuit is disclosed. The network includes an integrated coupling transformer having a secondary winding for coupling to a load and a primary winding for coupling to a source; a first integrated capacitive circuit controllably coupled across one of the primary and secondary windings and when so coupled operable to resonate with the integrated coupling transformer at a frequency in a first frequency band; and a second integrated capacitive circuit coupled across a second one of the primary and the secondary windings that is operable to resonate with the integrated coupling transformer at a frequency in a second frequency band. The method is in an IC and includes providing and coupling an input signal within alternatively a first frequency band and a second frequency band to a primary winding of an integrated coupling transformer; controlling an integrated switched capacitor network, coupled to the transformer, to provide a coupling network that is alternatively and respectively resonant at a first and second frequency within the first and second frequency band thus selectively providing an output signal at a secondary winding of the transformer; and down converting the output signal.

Integrated frequency selectable resonant coupling network and method thereof

An adjustable gain control (AGC) system with improved gain control accuracy and method thereof is disclosed. The system includes an offset circuit for providing an offset signal that is selectable; a gain setting source for providing a gain set signal that is dependent on a desired gain and the offset signal; and an AGC circuit, coupled to the offset signal and gain set signal, for providing a gain control signal, the AGC circuit compensating, according to the offset signal, the gain control signal for process variables corresponding to the AGC circuit to provide a plurality of predetermined gains for the amplifier that correspond, respectively, to a plurality of desired gains indicated by respective gain select signals.

Adjustable gain control system and method thereof

A circuit and method for producing a phase shifted quadrature signal (VOUT) from an in-phase signal (VIN). The in-phase signal (VIN) is applied to the control electrode of a voltage follower (121). The voltage follower (121) has a variable output resistance which combines with a capacitor (123) to delay the input signal (VIN) in accordance with the time constant formed by the variable output resistance and the capacitor (123). The variable output resistance is controlled by adjusting the bias current of the voltage follower (121) with a control signal.

Variable phase shifter and method

A circuit and method for reducing a phase error at the output terminal (48) of a multiplier circuit (41) is provided. The phase error arises when first and second input signals having asymmetric signal paths are multiplied in the multiplier circuit (41). A second multiplier circuit (42) multiplies the in-phase and quadrature signals and produces an output signal at an output terminal (49) which contains the phase error but with the opposite polarity as the phase error produced by the first multiplier circuit (41). The signals at the output terminals (48) and (49) are summed in a summing circuit (43) to produce a third output signal in which the phase error is canceled.

Circuit and method for correcting phase error in a multiplier circuit

An electronic device (10) comprises a copper integrated inductor (11) overlying other solid state components (31) of the device (10). Preferably, the copper inductor (11) is formed of plated copper to a thickness of several microns. The preferred integrated inductor (11) provides significant advantage over external inductors of the past with respect to simplicity of manufacture as well as system size and cost. Additionally, the preferred inductor (11) provides improved inductance per area, lower series resistance and higher Q values, relative to inductors of the past.

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Austin, TX, United States of America

Stephen W Dow