International Business Machines Corporation

Globalfoundries Inc.

King Abdulaziz City for Science and Technology

Stmicroelectronics Gmbh

S.o.i.tec Silicon on Insulator Technologies

Azur Space Solar Power Gmbh

Stephen W Bedell

Devendra K Sadana

Keith E Fogel

Ghavam G Shahidi

Ning Li

Davood Shahrjerdi

Bahman Hekmatshoartabari

Alexander Reznicek

Katherine Lynn Saenger

Joel Pereira De Souza

Paul Alfred Lauro

Ali Khakifirooz

John Albrecht Ott

Steven J Holmes

Bruce Bennett Doris

Pouya Hashemi

Karthik Balakrishnan

Huajie Chen

Cheng-Wei Cheng

Jeehwan Kim

Kangguo Cheng

Brent A Wacaser

Thomas N Adam

Frank Robert Libsch

Bing Dang

Kuen-Ting Shiu

Patryk Gumann

Hariklia Deligianni

Dominic Joseph Schepis

Wilfried Haensch

Josephine B Chang

Jack Oon Chu

Pranita Kulkarni

Yun Seog Lee

Ali Afzali-Ardakani

Judson Robert Holt

Harold John Hovel

Huilong Zhu

Effendi Leobandung

Nicolas J Loubet

Shu-Jen Han

Michael Patrick Chudzik

Chung-Hsun Lin

Martin Michael Frank

Teodor Krassimirov Todorov

Robert H Dennard

Steven John Koester

Jeffrey W Sleight

Shogo Mochizuki

Dechao Guo

Hemanth Jagannathan

Michael A Guillorn

Ruqiang Bao

Kerry Bernstein

Dirk Pfeiffer

Lubomyr Taras Romankiw

Huiming Bu

Xiao Hu Liu

Christos Dimitrios Dimitrakopoulos

Qiqing Christine Ouyang

Solomon Assefa

Robert L Wisnieff

Chun-Chen Yeh

Yurii A Vlasov

Johnathan E Faltermeier

Anirban Basu

Kathryn Turner Schonenberg

Mahadevaiyer Krishnan

James Bowler Hannon

Yann A Astier

Paul S Chang

Qiang Huang

Karen A Nummy

James R Kozloski

Guy M Cohen

Oleg Gluschenkov

Vijay Narayanan

Kevin K Chan

Dureseti Chidambarrao

Isaac Lauer

Theodore Gerard Van Kessel

Shreesh Narasimha

Damon B Farmer

Renee Tong Mo

Pranita Kerber

Sufi Zafar

Tze-Chiang Chen

Seyoung Kim

Conal Eugene Murray

Deborah A Neumayer

Min Yang

Nathan P Marchack

John Christopher Arnold

Kevin W Brew

William K Henson

Murat Kerem Akarvardar

Abhishek Dube

Jody Alan Fronheiser

Gen Pei Lauer

Zhibin Ren

One or more trenches in a silicon substrate have an electrically active surface at a trench base and metal layer disposed on the electrically active surface. Precursor materials are disposed and/or formed on the metal layer in the trench. An anode is patterned either exclusively in the 3D trench or in the 3D trench, sidewalls and field of the substrate, where the anode patterning transforms and/or moves the precursor materials in the trench into some novel compositions of matter and other final operational structures for the device, e.g. layers of metallic Lithium for energy storage and different concentrations of Lithium-silicon species in the substrate. A multi-faceted mechanism is disclosed for Al2O3 silicon interfacial additives. When the anode is patterned both in and outside the 3D wells, Al2O3 provides an for electron-conductive Li-metal interface that enables homogenous plating on both the insulated substrate field as well as active silicon trench base where Al2O3 acts as a barrier to Li—Si diffusion. When the anode is patterned only in the 3D trench, Al2O3 additive creates a robust, flexible, Li-permeable interface upon charge cycling, which preserves the 3D textured structure of the porous silicon anode. Additionally, the Al2O3 additive is mobilized deeper into the bulk silicon in parallel with Li+ and a conductive plasticizer upon progressive cycling—where the lithiated Al2O3 particles nucleate at defect sites and prevent mechanical degradation of the silicon anode through a combined bridge and spacer mechanism. By selecting different defined anode patterns to deposit on the 3D substrate, final operational characteristics, properties, structures, and charge storage performance for the device can be predictably designed and manufactured.

Energy storage method using aluminum oxide protected lithium metal tunable 3D silicon batteries

A vertical Josephson Junction (JJ) qubit device that is fabricated from crystalline silicon material is provided. The JJ device has a substrate of epitaxial silicon, a lower superconducting electrode that is a superconducting region of the epitaxial silicon and an upper superconducting electrode of a metallic superconductor. The JJ device also has a junction layer. A section of the junction layer between the lower and upper superconducting electrodes forms a junction of the JJ device. Resonator and/or capacitor wiring of the JJ device is also fabricated using the metallic superconductor. The superconducting region is epitaxial silicon that is doped or implanted with boron or gallium. The substrate, the junction layer, and the implanted epitaxial silicon share a contiguous crystalline structure.

Vertical silicon Josephson Junction device for qubit applications

A deposition system includes a deposition source and a scanning stage disposed within a deposition path of the deposition source. The scanning stage includes a support platform configured to support a wafer thereon, and a mechanical actuator coupled to the support platform. The mechanical actuator is configured to translate the support platform with respect to the deposition source. The deposition system includes a proximity mask disposed within the deposition path of the deposition source between the deposition source and the scanning stage, the proximity mask defining a slit. The deposition system includes a controller in communication with the scanning stage, the controller configured to control the mechanical actuator to translate the wafer with respect to the slit such that an angle of deposition remains substantially constant. In operation, the proximity mask prevents deposition source material having a trajectory that is out of alignment with the slit from contacting the wafer.

Cluster tool for production-worthy fabrication of Dolan bridge quantum Josephson junction devices

Compound semiconductor and silicon-based structures are epitaxially formed on semiconductor substrates and transferred to a carrier substrate. The transferred structures can be used to form discrete photovoltaic and light-emitting devices on the carrier substrate. Silicon-containing layers grown on doped donor semiconductor substrates and compound semiconductor layers grown on off-cut semiconductor substrates form elements of the devices. The carrier substrates may be electrically insulating substrates or include electrically insulating layers to which photovoltaic and/or light-emitting structures are bonded.

Device integration using carrier wafer

A method of forming a solid-state lithium ion rechargeable battery may include depositing a metal layer onto a top surface of a substrate, depositing a handle layer onto a top surface of the metal layer, wherein a portion of the handle layer overlaps the metal layer and the substrate, spalling a portion of the substrate thereby forming a spalled substrate layer, porosifying the spalled substrate layer thereby forming a porous substrate layer, depositing an electrolyte layer onto a top surface of the porous substrate layer, wherein the electrolyte layer is in direct contact with the porous substrate layer, and depositing a cathode onto a top surface of the electrolyte layer. The method may include depositing a cathode contact layer onto a top surface of the cathode, wherein the cathode contact layer is in direct contact with the cathode. The porous substrate layer may be made of silicon.

Solid state lithium ion rechargeable battery

A semiconductor device structure and method for forming the same is disclosed. The structure incudes a silicon substrate having at least one trench disposed therein. An electrical and ionic insulating layer is disposed over at least a top surface of the substrate. A plurality of energy storage device layers is formed within the one trench. The plurality of layers includes at least a cathode-based active electrode having a thickness of, for example, at least 100 nm and an internal resistance of, for example, less than 50 Ohms/cm. The method includes forming at least one trench in a silicon substrate. An electrical and ionic insulating layer(s) is formed and disposed over at least a top surface of the silicon substrate. A plurality of energy storage device layers is formed within the trench. Each layer of the plurality of energy storage device layers is independently processed and integrated into the trench.

Fabrication of all-solid-state energy storage devices

A method includes implanting an implantable biosensor within a subject where the implantable biosensor has an array of light sources and an array of light detectors, activating the array of light sources to direct light signals at a targeted tissue site in the subject, capturing, with the light detectors, the light signals reflected off the targeted site, calculating a roundtrip propagation time for each of the light signals and comparing the roundtrip propagation time for each of the light signals against previous calculated respective roundtrip propagation times to determine an occurrence of a change in the targeted tissue site.

LIDAR implantable biosensor for imaging biological tissue

A gated Josephson junction includes a substrate and a vertical Josephson junction formed on the substrate and extending substantially normal the substrate. The vertical Josephson junction includes a first superconducting layer, a semiconducting layer, and a second superconducting layer. The first superconducting layer, the semiconducting layer, and the second superconducting layer form a stack that is substantially perpendicular to the substrate. The gated Josephson junction includes a gate dielectric layer in contact with the first superconducting layer, the semiconducting layer, and the second superconducting layer at opposing side surfaces of the vertical Josephson junction, and a gate electrically conducting layer in contact with the gate dielectric layer. The gate electrically conducting layer is separated from the vertical Josephson junction by the gate dielectric layer. In operation, a voltage applied to the gate electrically conducting layer modulates a current through the semiconducting layer of the vertical Josephson junction.

Superconductor-semiconductor Josephson junction

A method of producing a quantum circuit includes forming a mask on a substrate to cover a first portion of the substrate, implanting a second portion of the substrate with ions, and removing the mask, thereby providing a nanowire. The method further includes forming a first lead and a second lead, the first lead and the second lead each partially overlapping the nanowire. In operation, a portion of the nanowire between the first and second leads forms a quantum dot, thereby providing a quantum dot Josephson junction. The method further includes forming a third lead and a fourth lead, one of the third and fourth leads partially overlapping the nanowire, wherein the third lead is separated from the fourth lead by a dielectric layer, thereby providing a Dolan bridge Josephson junction. The nanowire is configured to connect the quantum dot Josephson junction and the Dolan bridge Josephson junction in series.

Combined Dolan bridge and quantum dot Josephson junction in series

Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate a suspendeddevice comprising an ion implant defined nanorod in a semiconducting device are provided. According to an embodiment, a quantum computing device can comprise adevice coupled to an ion implanted region. The quantum computing device can further comprise an encapsulation film coupled to the ion implanted region and a substrate layer. The encapsulation film suspends thedevice in the quantum computing device.

Ion implant defined nanorod in a suspended Majorana fermion device

A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.

Three-dimensionally stretchable single crystalline semiconductor membrane

Systems and techniques that facilitate quantum tuning via permanent magnetic flux elements are provided. In various embodiments, a system can comprise a qubit device. In various aspects, the system can further comprise a permanent magnet having a first magnetic flux, wherein an operational frequency of the qubit device is based on the first magnetic flux. In various instances, the system can further comprise an electromagnet having a second magnetic flux that tunes the first magnetic flux. In various cases, the permanent magnet can comprise a nanoparticle magnet. In various embodiments, the nanoparticle magnet can comprise manganese nanoparticles embedded in a silicon matrix. In various aspects, the system can further comprise an electrode that applies an electric current to the nanoparticle magnet in a presence of the second magnetic flux, thereby changing a strength of the first magnetic flux.

Quantum tuning via permanent magnetic flux elements

Methods of forming a controllable resistive element include forming source and drain regions in a substrate. A battery stack is formed on a substrate between the source and drain regions. Respective anode and cathode electrical connections are formed to the battery stack. Respective source and drain electrical connections are formed.

Battery-based neural network weights

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Wappingers Falls, NY, United States of America

Stephen W Bedell