Advanced Micro Devices Corporation

International Business Machines Corporation

Ati Technologies Ulc

Globalfoundries Inc.

Stephen Victor Kosonocky

Azeez Jennudin Bhavnagarwala

John P Petry

Miguel Rodriguez

Alexander J Branover

Benjamin Tsien

Indrani Paul

Mihir Shaileshbhai Doctor

Thomas James Gibney

Christopher T Weaver

Suhwan Kim

Daniel Ray Knebel

Mikhail Rodionov

Joyce Cheuk Wai Wong

Samuel D Naffziger

Kerry Bernstein

Ravinder Reddy Rachala

Rajiv V Joshi

Kaushik Mazumdar

Louis L Hsu

Sampath Purushothaman

Randy William Mann

Li-Kong Wang

Norman Jay Rohrer

Paul David Kartschoke

Edward J Nowak

Paul William Coteus

Kenneth Parker Rodbell

Philip George Emma

Robert H Dennard

Wei Hwang

Ruchir Puri

Russell J Schreiber

Peter Anthony Sandon

Mark B Ritter

Ljubisa Bajic

Allan Mark Hartstein

Wing Kin Luk

Spencer Montgomery Gold

Sam Gat-Shang Chu

Thomas Edward Cook

Steven Kommrusch

Kevin Wilson Warren

Peter Edwin Cottrell

John E Andersen

Arthur A Bright

J Adam Butts

Ian R Govett

Carl John Radens

Terence B Hook

John Atkinson Fifield

Silvia Melitta Mueller

Leland Chang

Satyanarayana Venkata Nitta

Larry David Hewitt

Kevin John Nowka

Vydhyanathan Kalyanasundharam

Keith Aelwyn Jenkins

Harry S Barowski

Yasunao Katayama

Seiji Munetoh

John J Wuu

Jae-Joon Kim

David Meltzer

Michael A Nix

David James Frank

Warren Anderson

Edward J McLellan

Richard Martin Born

Keith Robert Williams

William A Klaasen

Gary S Ditlow

Sebastien Nussbaum

Carlin D Cabler

Chintan S Patel

Jochen Preiss

Saiful Islam

Grady L Giles

Roger Paul Gregor

Stephen C Ennis

Arun Sundaresan Iyer

Carson Donahue Henrion

Visvesh S Sathe

Jeffery Howard Oppold

Brian Chan Monwai

Subhrajit Bhattacharya

Michael L Golden

David Hugh McIntyre

Kevin Geoffrey Stawiasz

Jeffrey H Oppold

Girish Anathahalli Singrigowda

Erwin B Cohen

Donald A Priore

Pravesh Gupta

Stephen J Barnfield

Gregory Kengho Chen

Amlan Ghosh

Karthik Natarajan

Peter Thomas Hardman

Alexander W Schaefer

Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain that is powered off in the power management state. In some implementations, the power domain is powered off in the mode. In some implementations, the device is powered on in the mode via a power rail that is specific to the mode. In some implementations, the entry condition of the mode includes an amount of data stored for display in a display buffer falling below a threshold amount.

On-demand IP initialization within power states

Devices and methods for cache prefetching are provided. A device is provided which comprises a quality of service (QOS) component having first assigned registers used to store data to execute a program, a plurality of non-QOS components having second assigned registers used to store data to execute the program and a power management controller, in communication with the QOS component and the non-QOS components. The power management controller is configured to issue fences for the non-QOS components when it is determined that one or more of the non-QOS components are idle, issue a fence for the QOS component when the fences for the non-QOS components are completed and enter a reduced power state when the fences for the non-QOS components and the fence for the QOS component are completed.

Device and method for two-stage transitioning between reduced power states

A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.

Method and apparatus for managing power states

A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response to receiving an acknowledgement from the component of a request from the power management controller to remove power to the component, and executes a process to exit the component from the reduced power state in response to the component being active.

Device and method for efficient transitioning to and from reduced power state

Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.

Using a hardware-based controller for power state management

A method and apparatus for managing a controller includes indicating, by a processor of a first device, to the controller of a second device to enter a second power state from a first power state. The controller of the second device responds to the processor of the first device with a confirmation. The processor of the first device transmits a signal to the controller of the second device to enter the second power state. Upon receiving a wake event, the controller of the second device exits the second device from the second power state to the first power state.

Method and apparatus for managing a controller in a power down state

A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.

Fast droop detection circuit

Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.

Device and method for reducing save-restore latency using address linearization

An oscillator circuit is provided that adapts to voltage supply variations. The circuit first and second delays lines connected inputs of an edge detector, one delay line supplied by a reference voltage and the other with a drooping supply voltage. The edge detector generates an output clock based on a relationship between the inputs. The output clock applied to the signal inputs of the first and second delay lines. The output clock has a voltage dependent frequency performance curve with a slope dependent at least on the second delay line delay and a delay of the edge detector. At least one of the first delay line, the second delay line, and the edge detector delay are adjusted to change the slope of the performance curve.

Adaptive DCO VF curve slope control

A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.

Performance management during power supply voltage droop

A multiply-accumulate computation is performed using digital logic circuits. To perform the computation, a plurality of target signals are received at a respective plurality of ripple counters. The counter outputs of the respective ripple counters are scaled by setting stop count values. Counter outputs of the respective ripple counters are adjusted with respective constant values by setting counter reset values at the respective ripple counters. Each count pulses of the target signals for an adjusted period. The count values of the ripple counters are summed. The results may be used to calculate an average value for an adaptive voltage and frequency scaling process.

Time domain multiply and accumulate system

A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.

Droop detection and control of digital frequency-locked loop

An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.

Adaptive oscillator for clock generation

Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.

A power supply monitor includes a delta-sigma modulator including an input receiving a binary number and an output providing a pulse-density modulated signal, the delta-sigma modulator operable to scale the pulse-density modulated signal based on the binary number. A fast droop detector circuit includes a level shifter providing the modulated signal referenced to a clean supply voltage. A lowpass filter is coupled between the level shifter and a comparator. The comparator produces a droop detection signal at said output responsive to a monitored supply voltage dropping below a predetermined level relative to the filtered signal.

Flexible circuit for droop detection

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Fort Collins, CO, United States of America

Stephen Victor Kosonocky