International Business Machines Corporation

International Business Corporation

Stephen Thomas Quay

Charles Jay Alpert

Zhuo Li

Jiang Hu

Ying Zhou

Tuhin Mahmud

Rama Gopal Gandham

Lakshmi Narasimha Reddy

Chin Ngai Sze

Gi-Joon Nam

Yaoguang Wei

Gustavo Enrique Tellez

Robert Mahlon Averill, Iii

Jose L P Neves

Anirudh Devgan

Carol Ivash Gabele

Milos Hrkic

Paul Gerard Villarrubia

Parsotam Trikam Patel

Eric Jason Fluhr

Bijian Chen

Arvind K Karandikar

Jose Luis Neves

Joachim Gerhard Clabes

Chandramouli V Kashyap

Alexander K Spencer

William E Dougherty, Jr

Andrew James Sullivan

Jose Luis Pontes Correia Neves

Clay Chip Smith

Chong-Nuen Chu

Jean-Paul Watson

Glenn R Bee

Paul G Villarrubla

A method a system include obtaining a master list of layer traits including wire codes, each of the wire codes indicating a width of a corresponding wire, and including a maximum reach length of the corresponding wire and a time of flight (TOF) through the corresponding wire. The method also includes processing the master list of the layer traits to obtain a final list of the layer traits, the final list of the layer traits having fewer entries than the master list of the layer traits and being in a ranked order. A metric is calculated for each adjacent pair of the layer traits in the final list of layer traits. The final list of the layer traits and the corresponding metric is used to assign the corresponding wires to different interconnects among components of an integrated circuit.

Automatic layer trait generation and promotion cost computation

Methods and systems for improving the performance of a computer performing an electronic design. One or more nets of a netlist are sorted based on an amount of slack and a net of the one or more nets that is unprocessed and that has a least amount of slack is selected as a current target net. A layer of a higher bucket that is unprocessed for the currently selected target net is selected, the higher bucket being higher than a bucket of the current target net. A determination of whether capacity is available to route the current target net on the selected layer of the higher bucket is made and the current target net is routed on the selected layer of the higher bucket in response to capacity being available. One or more nets that are competing for resources with the current target net on the selected layer of the higher bucket are identified as candidate nets in response to capacity not being available.

Net layer promotion with swap capability in electronic design

Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

Integrated circuit buffering solutions considering sink delays

A mechanism is provided for addressing coupled noise-based violations. For each net in an integrated circuit (IC) design, a determination is made as to whether an associated delta wire delay is below a predetermined threshold. Responsive to the associated delta wire delay failing to be below the predetermined threshold, a subset of nets is formed. For each net in the subset of nets, a stage delay side model of the net is adjusted to emulate a noise impact on timing of the net and an optimization is applied using the stage delay side model of the net. A full retiming of the set of nets is then performed. For each net in the subset of nets a determination is made as to whether the net has degraded slack and, responsive to the net having degraded slack, the applied optimization is backed out.

Addressing coupled noise-based violations with buffering in a batch environment

Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.

Automatic generation of wire tag lists for a metal stack

Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.

Early design cycle optimization

A system, process, etc. according to some embodiments, which includes operations that include selecting one of a plurality of solutions ('selected solution') for optimization of an integrated circuit design during physical synthesis. The operations can further include performing on the selected solution a fast evaluation of a specific metric without updating design documents (e.g., without updating a netlist or metric map). If the evaluation of the specific metric is non-satisfactory, then the candidate solution is rejected. If the evaluation of the specific metric is satisfactory, then a design document is updated and a full evaluation of the specific metric (and other metrics) can be performed.

Physical synthesis optimization with fast metric check

Early design cycle optimzation

A method, system, and computer program product for timing driven routing in a design of an integrated circuit (IC) are provided in the illustrative embodiments. A router application executing in a data processing system performs a pre-global routing optimization of the design. A plurality of wirelength target constraints are set on a plurality of subsets of a set of nets in the design. Global routing is performed on the design. The design is adjusted using wires placed in the design during the global routing. A priority is assigned to each net in the set of nets. Detailed routing is performed on the design.

Timing driven routing in integrated circuit design

A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determination is made as to whether the net is routable through a cell in a plurality of cells using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold. Responsive to net being able to be routed through the cell with the coupling capacitance being equal to or below the threshold, the net is assigned to at least one track within the cell. Responsive to all nets in the new IC design being routed, a new IC design is generated.

Resolving global coupling timing and slew violations for buffer-dominated designs

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Austin, TX, United States of America

Stephen Thomas Quay