Intel Corporation

Stephen T Palermo

Scott P Dubal

Edwin Verplanke

John Joseph Browne

David Sonnier

Chris MacNamara

William G Burroughs

Niall D McDonnell

Kapil Sood

Jr-Shian Tsai

Michael Hingston McLaughlin Bursell

Rahul R Shah

Srihari Makineni

Ned M Smith

Andrew J Herdrich

Francesc Guim Bernat

Kshitij Arun Doshi

Hassnaa Moustafa

Eliezer Tamir

Anjali Singhai Jain

Glen J Anderson

Chittabrata Ghosh

Rita H Wouhaybi

Rajesh M Sankaran

Tsung-Yuan Charles Tai

Ravishankar Iyer

Giuseppe Beppe Raffa

Srikathyayani Srikanteswara

Lokpraveen B Mosur

Shao-Wen Yang

Yen-Cheng Liu

Timothy Verrall

Iosif Gasparakis

Mrittika Ganguli

Ben-Zion Friedman

Karthik Veeramani

Hang T Nguyen

Parthasarathy Sarangam

Thomas E Willis

Stephen R Van Doren

Vasudevan Srinivasan

Marcos Emanuel Carranza

Ilango S Ganga

Lenitra M Durham

Rupin H Vakharwala

Rahul C Shah

Yi Zhang

Jesse C Brandeburg

Shrikant M Shah

Valerie J Parker

Abhishek Khade

Pradeepsunder Ganesh

Sarita Maini

Neelam Chandwani

Udayan Mukherjee

Trevor Cooper

Rajesh Gadiyar

Gage Eads

Abhirupa Layek

Pierre Laurent

David K Cassetti

Patrick Fleming

Sailesh Bissessur

Hari K Tadepalli

Atul Kwatra

Gerald Alan Rogers

Smita Kumar

Namakkal N Venkatesan

Chetan Hiremath

Adwait Purandare

Naveen Lakkakula

Julius Yuli Mandelblat

Tomasz Kantecki

Jeffrey D Chamberlain

Meng Shi

Addicam V Sanjay

Abhilasha Bhargav-Spantzel

Nikhil Gupta

Andrew Cunningham

Thijs Metsch

Bruce Richardson

Neal Conrad Oliver

Mark D Gray

Cesar Martinez-Spessot

Reese Bowes

Pete A Denman

Valerie J Young

Christopher MacNamara

Rebecca Chierichetti

Rashmin N Patel

Eric R Wehage

Alexander J Leckey

Jose A Avalos

Sean Harte

Benjamin Bair

Pinkesh J Shah

Uzair Qureshi

Krishnamurthy Jambur Sathyanarayana

Soo Jin Tan

Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

Dynamic load balancing for multi-core computing environments

An example apparatus includes a workload analyzer to determine an application ratio associated with the workload, the application ratio based on an operating frequency to execute the workload, a hardware configurator to configure, before execution of the workload, at least one of (i) one or more cores of the processor circuitry based on the application ratio or (ii) uncore logic of the processor circuitry based on the application ratio, and a hardware controller to initiate the execution of the workload with the at least one of the one or more cores or the uncore logic.

Systems, methods, and apparatus for workload optimized central processing units (CPUS)

Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

Hardware queue scheduling for multi-core computing environments

Various approaches for the deployment and coordination of inter-satellite communication pathways, defined for use with a satellite non-terrestrial network, are discussed. Among other examples, such inter-satellite communication pathways may be identified, reserved, allocated, and used for ultra-low-latency communication purposes.

Ultra-low latency inter-satellite communication links

Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores. These capabilities enhance performance and provides flexibility to handle a variety of applications requiring use of advanced AVX/AMX instructions to support accelerated workloads.

Frequency scaling for per-core accelerator assignments

Various approaches for the deployment and use of communication exclusion zones, defined for use with a satellite non-terrestrial network (including within a low-earth orbit satellite constellation), are discussed. In an example, defining and implementing a non-terrestrial communication exclusion zone includes: calculating based on a future orbital position of a low-earth orbit satellite vehicle, an exclusion condition for communications from the satellite vehicle; identifying, based on the exclusion condition and the future orbital position, a timing for implementing the exclusion condition for the communications from the satellite vehicle; and generating exclusion zone data for use by the satellite vehicle, the exclusion zone data indicating the timing for implementing the exclusion condition for the communications from the satellite vehicle.

Satellite 5G terrestrial and non-terrestrial network interference exclusion zones

Various approaches for the packet processing, and the use of templates for generating modification commands for packet processing, are discussed herein. In an example, operations performed by network packet processing circuitry include: obtaining a stream of packets; obtaining a packet modification template that provides at least one command to insert content within the packets and change the packets according to an output format of a network protocol; receiving parameters to modify the packet modification template; and applying the packet modification template to modify the packets. In further examples, application of the packet modification template is performed using multiple processing components arranged in parallel groups of serial pipelines, each of the serial pipelines applying a portion of the packet modification template within at least a first stage and a second stage in each of the serial pipelines.

Network processor with command-template packet modification engine

In one embodiment, an apparatus comprises a memory and a processor. The memory is to store sensor data, wherein the sensor data is captured by a plurality of sensors within an educational environment. The processor is to: access the sensor data captured by the plurality of sensors: identify a student within the educational environment based on the sensor data: detect a plurality of events associated with the student based on the sensor data, wherein each event is indicative of an attention level of the student within the educational environment: generate a report based on the plurality of events associated with the student; and send the report to a third party associated with the student.

Interactive environments using visual computing and immersive reality

An apparatus operating as a certificate authority (CA) is described. The apparatus can perform operations including receiving, from a plurality of requesting devices, a request to join a group. The request can include identification information for the group and attestation evidence for the plurality of requesting devices. Responsive to receiving the request, the apparatus can provide a group certificate for the group to the plurality of requesting devices.

Privacy protected autonomous attestation

Examples described herein relate to an encoder circuitry to apply one of multiple lossless data compression schemes on input data. In some examples, to compress input data, the encoder circuitry is to utilize a search window size and number of searches based on an applied compression scheme. In some examples, content of a memory is reconfigured to store data corresponding to a search window size of the applied compression scheme. In some examples, an applicable hash function is configured based on the applied compression scheme. In some examples, a number of searches are made for a byte position. In some examples, the encoder circuitry includes a hash table look-up and a bank decoder. In some examples, the hash table look-up is to generate a hash index to identify an address of an entry in the search window. In some examples, the bank decoder is to select a bank based on the hash index.

Compression engine with configurable search depths and window sizes

Examples described herein relate to an apparatus comprising a central processing unit (CPU) and an encoding accelerator coupled to the CPU, the encoding accelerator comprising an entropy encoder to determine normalized probability of occurrence of a symbol in a set of characters using a normalized probability approximation circuitry, wherein the normalized probability approximation circuitry is to output the normalized probability of occurrence of a symbol in a set of characters for lossless compression. In some examples, the normalized probability approximation circuitry includes a shifter, adder, subtractor, or a comparator. In some examples, the normalized probability approximation circuitry is to determine normalized probability by performance of non-power of 2 division without computation by a Floating Point Unit (FPU). In some examples, the normalized probability approximation circuitry is to round the normalized probability to a decimal.

Normalized probability determination for character encoding

Various systems and methods for implementing a multi-access edge computing (MEC) based system to realize 5G Network Edge and Core Service Dimensioning using Machine Learning and other Artificial Intelligence Techniques, for improved operations and usage of computing and networking resources, and are disclosed herein. In an example, processing circuitry of a compute node on a network is used to analyze execution of an application to obtain operational data. The compute node then may modularize functions of the application based on the operational data to construct modularized functions. A phase transition graph is constructed using a machine-learning based analysis, the phase transition graph representing state transitions from one modularized function to another modularized function, where the phase transition graph is used to dimension the application by distributing the modularized functions across the network.

5G network edge and core service dimensioning

Various systems and methods for implementing an edge computing system to realize 5G network slices with blockchain traceability for informed 5G service supply chain are disclosed. A system configured to track network slicing operations includes memory and processing circuitry configured to select a network slice instance (NSI) from a plurality of available NSIs based on an NSI type specified by a client node. The available NSIs uses virtualized network resources of a first network resource provider. The client node is associated with the selected NSI. The utilization of the network resources by the plurality of available NSIs is determined using an artificial intelligence (AI)-based network inferencing function. A ledger entry of associating the selected NSI with the client node is recorded in a distributed ledger, which further includes a second ledger entry indicating allocations of resource subsets to each of the NSIs based on the utilization.

5G network slicing with distributed ledger traceability and resource utilization inferencing

Growing community of inventors

Chandler, AZ, United States of America

Stephen T Palermo