Advanced Micro Devices Corporation

Legerity, Inc.

Stephen T Novak

John C Peck, Jr

Stephan Rosner

Ralf Flemming

Scott Waldron

William F Kern

Matthias Baer

Hong-Yi Chen

Jörg Winkler

Ralf Fleming

Jorg Winkler

A wireless computer system () is formed to have a host section () and a wireless hardware section (). A first portion of a transmission frame is formed in system memory () of a host section () and a second portion of the transmission frame is formed in the wireless hardware section (). The wireless hardware section () begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory () into the wireless hardware section ().

Wireless computer system with queue and scheduler

A wireless computer system () is formed to have a host section () and a wireless hardware section (). A first portion of a transmission frame is formed in system memory () of a host section () and a second portion of the transmission frame is formed in the wireless hardware section (). The wireless hardware section () begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory () into the wireless hardware section (). Bus latencies are masked by at least overlapping transmitting the first portion of the transmit frame while downloading the second portion.

Wireless computer system with latency masking

The invention relates to a method and an apparatus for receiving and transmitting asynchronous transfer mode (ATM) cell streams over a bus. The invention provides a method for receiving ATM cells in a host from a client over a bus, comprising the steps of determining whether an ATM cell in a first storage device within the client is ready to be transferred over the bus to a second storage device within the host, preventing overflow of the second storage device by calculating a first available cell space in the second storage device as a function of a write value, a read value image and a size value of the second storage device, and transferring an ATM cell from the first storage device to the second storage device.

Method and apparatus for controlling ATM streams

The invention relates to an apparatus and a method for accessing memories having a time-variant response over a PCI bus by using two-stage DMA transfers. The invention provides a method for executing a read request over a PCI bus by transferring the requested data from a main memory of a PCI card to a device located on the PCI bus, comprising the steps of obtaining an access request from a read access queue, transferring, by a first DMA transfer, the requested data from the main memory to a buffer memory on the PCI card, and transferring, by a second DMA transfer, the data from the buffer memory to the device.

Method and apparatus for accessing memories having a time-variant response over a PCI bus by using two-stage DMA transfers

A memory controller for a computer memory which decodes memory requests into individual primitive memory operations which are then queued into separate operation queues. The operation queues independently issue their queued primitive memory operations to the memory in order to initiate the memory request. The operation queues monitor and adhere to timing and ordering dependencies between the primitive memory operations that are queued and those that have already been transmitted to the memory. Once a primitive memory operation is transmitted to the memory, it is dequeued from its respective operation queue. A control queue monitors the progress of the primitive memory operations transmitted to the memory, completes the initiated memory request and provides timing and ordering dependency data to the operation queues.

Queue based memory controller

A control queue for predicting, tracking and completing memory requests initiated by a memory controller in a computer memory. The control queue is loaded with the cycle by cycle control data necessary to complete the memory request. The control queue shifts its contents from one entry to the next on every clock cycle to the bottom entry of the queue. The control data from the bottom entry is used to generate signals and data to control the operation of the data path for the current clock cycle. The control queue also tracks and provides operational and timing dependency data to the memory controller so that operations can be initiated properly.

Queue based data control mechanism for queue based memory controller

A memory controller for a dynamic random access memory which pre-charges active banks in a particular chip select when an eight quadword access is made to another bank within that same chip select. When the memory controller detects an eight quadword access which is a page hit or page miss within the same chip select, the memory controller will look for any other active banks on that chip select. If there is another active bank other than the bank being accessed by the eight quadword access, the memory controller will attempt to transmit a pre-charge operation to that bank in the clock cycle immediately following the acceptance of the eight quadword access.

Method and apparatus for optimizing memory performance with opportunistic pre-charging

A memory controller for a dynamic random access memory having counters for each chip select in the memory. The counters are incremented at a fixed interval. Programmable threshold values are provided which, when compared with the counters, indicate to the memory controller when a refresh should be opportunistically attempted and when a refresh is urgently required. The memory controller then either attempts to find an idle cycle to send the opportunistic refresh or blocks memory accesses to create a window for an urgently needed refresh. Once a refresh is sent to the memory, the appropriate counter is decremented accordingly.

Method and apparatus for optimizing memory performance with

A microprocessor having a segment descriptor cache that holds data obtained from a segment descriptor table contained in an external memory and a separate data cache that holds data obtained from portions of the external memory other than the segment descriptor table.

Growing community of inventors

Agoura, CA, United States of America

Stephen T Novak