Intel Corporation

Stephen T Flannagan

Edmund A Reese

Dieter W Spaderna

Jonathan Nick Spitz

Roger I Kung

Perry H Pelley, Iii

Robert S Riley

Douglas J Covert

A dynamic MOS random-access memory is described which includes a circuit for permitting checking of the on chip refresh counter. The memory also includes a refresh generator, the frequency of which automatically varies to compensate for temperature variations. Other innovations include an arbitration circuit, a hidden refresh function and unique accessing of redundant lines.

Multiple bit dynamic random-access memory

A method for testing an MOS, dynamic random-access memory employing full capacitance dummy cells is described. During probe testing a potential higher than the reference potential is applied to the dummy cells when reading binary zeroes from the memory and a potential lower than the reference potential is applied to the dummy cells when reading binary zeroes from the memory. This testing procedure detects weak cells and amplifiers and helps present the packaging of defective parts. In addition, a simplified means for programming redundant elements is described which requires substantially less substrate area than previous methods.

Testing method and apparatus for dram

Multiple bit output dynamic random-access memory

An MOS dynamic RAM organized in a byte-wide arrangement is described. An internal bus is used for multiplexed column address signals and data. Other multiplexing reduced the lines associated with the input/output circuits. A unique power-on circuit automatically resets clock generators if they are not operative after power is applied.

Byte-wide dynamic RAM with multiplexed internal buses

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Beaverton, OR, United States of America

Stephen T Flannagan