Intel Corporation

Stephen T Chambers

Mark T Bohr

Richard E Green

Shahriar S Ahmed

Anand S Murthy

Richard G Taylor

Robert S Chau

Valery M Dubin

Leopoldo D Yau

Andrew W Ott

Dan S Lavric

Chan-Hong Chern

Christine Hau-Riege

Brian J Brown

Stephen T Luce

The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Super self-aligned collector device for mono-and hetero bipolar junction transistors, and method of making same

The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

Self aligned compact bipolar junction transistor layout and method of making same

A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.

Enhancement of an interconnect

Self aligned compact bipolar junction transistor layout, and method of making same

Super self-aligned collector device for mono-and hetero bipolar junction transistors and method of making same

The present invention provides embodiments of methods and devices for the suppression of copper hillocks. Copper hillocks are suppressed by capping the copper layer with a dielectric film before any significant growth of copper hillocks can begin using a ramped temperature dielectric deposition process. Copper hillocks are also suppressed by doping a copper layer with a dopant that will constrain the grain size of the copper during subsequent processing. These methods are applicable to the construction of MIM capacitors and interconnect structures.

Methods and devices for the suppression of copper hillock formation

A method of fabricating a copper-containing structure, preferably within a microelectronic device, including a rapid temperature ramp from about 20 degrees Celsius up to between about 300 and 500 degrees Celsius, preferably about 400 degrees Celsius, at a rate of between about 20 and 60 degrees Celsius per second, preferably about 40 degrees Celsius per second.

Fast ramp anneal for hillock suppression in copper-containing structures

Super self-aligned collector device for mono-and hetero bipolar junction transistors

A BiCMOS process where a base region is formed in a relatively highly doped n-type substrate region. Boron is implanted at two different energy levels to form the base region and a counter doped n region near the base collector junction to prevent impact ionization.

BiCMOS process for counter doped collector

A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.

Integrated dual layer emitter mask and emitter trench for BiCMOS

BICMOS process for counter doped collector

Method of making emitter trench BiCMOS using integrated dual layer

A process of forming an emitter of a bipolar transistor is described. Dopants of a first conductivity type is implanted in the substrate to form the base. Dopants of a second conductivity type is then implanted into the base region to form a substrate emitter region. A polysilicon layer is then deposited over the substrate emitter and doped to form the doped polysilicon layer. An outdiffusion step follows to link the doped polysilicon layer to the substrate emitter.

Growing community of inventors

Portland, OR, United States of America

Stephen T Chambers