Unisys Corporation

Stephen Sutter

David P Williams

Chad M Sonmore

Kelvin S Vartti

James A Williams

Robert Marion Malek

Robert H Andrighetti

Conrad S Shimada

Marshall R Dew

Robert Norman Anderson

Howard Huy P Tran

Jason D Lanfield

A manner for judiciously snooping or otherwise monitoring bus operations associated with maintaining cache or other memory coherency in a computing system. A bus snoop information storage mode is established that identifies information pertaining to the bus snoop operations used to maintain memory coherency. The bus snoop information storage mode is selectable, relative to possible other modes. When the bus snoop information storage mode is activated, the information pertaining to the bus snoop operations occurring in connection with bus snoop stall cycles is disregarded, while the current state of the information pertaining to the bus snoop operations upon completion of the bus snoop operations is stored.

System and method for selectively storing bus information associated with memory coherency operations

A computing system with a mode-selectable bus interface. In one embodiment, the computing system includes a system bus, a processor coupled to the bus via an interface unit, and a controller coupled to the bus. The system bus implements one of a first and a second system bus protocols. The interface unit is compatible with the first system bus protocol in a first selectable mode and the second system bus protocol in a second selectable mode, and the controller is compatible with one of the system bus protocols. A mode register is coupled to the interface unit, and the interface unit selects the first mode responsive to a first value of the mode register and selects the second mode responsive to a second value of the mode register. A scan controller is coupled to the mode register for scanning a value into the mode register.

Dual mode capability for system bus

An improved system and method are provided for initializing memory in a data processing system. According to one aspect of the invention, a 'page zero' instruction is provided that may be executed by an Instruction Processor to initiate memory initialization. Upon instruction execution, the IP issues one or more page zero requests using a background interface of the IP. In one embodiment, each request results in the initialization of a page of memory. While page zero requests are issued over the background interface, the IP may continue issuing other read and write requests to memory over a primary interface of the IP.

System and method for initializing memory within a data processing system

A system for use in transferring data packets across different clock domains using an input data register for receiving a block of data packets with the input data register and a plurality of interface registers located in the first clock domain for transferring a block of data packets from the input register to a second clock domain in response to a request signal with the system prioritizing the transfer of multiple data packets within the block of data packets by length in order to transfer the longer word packets first and the shorter word packets last with the shortest word packets within the block bundled together and simultaneously transferring across an asynchronous interface.

System for data transfer across asynchronous interface

A system and method for transmitting commands from one or more input/output devices to a memory is provided. An identification tag is appended to each command to define the command as either a read or write command. The read commands are separated from the write commands based on the state of the identification tag, and the read and write commands are separately queued. The read commands are stored in a first command queue, and the write commands are stored in a second, separate, command queue. The read commands in the first command queue are successively transferred to the memory upon completion of the current memory read function, and the write commands in the second command queue are successively transferred to the memory upon completion of the current memory write function. The transfer of the read and write commands is independent.

Optimized input/output memory access request system and method

A method and apparatus for efficiently reading a day clock and storing the value into main storage. An advantage is that the memory storage command can request the main storage control to read a current day clock value and store the value into a main storage location specified by the requesting processor while allowing the requesting processor to continue processing other commands. A further advantage is that the requesting processor does not have to wait for the return of a day clock value or the generation of a main storage write request which may reduce the number of main storage I/O bus requests and bus transfer cycles over that normally required to transfer the day clock value to the requesting processor and then back to main storage.

Growing community of inventors

Osseo, MN, United States of America

Stephen Sutter