Qualcomm Incorporated

Stephen Simmonds

Sanjay K Jha

Nicholas K Yu

Safi Khan

Jalal Ahmad Elhusseini

Parag Arun Agashe

Madan Krishnappa

Sajjad Pagarkar

Ashwin Rabindranath

Sagar Digwalekar

Sanjay c/o Qualcomm Incorporated Jha

Nicholas K c/o Qualcomm Incorporated Yu

Jalal c/o Qualcomm Incorporated Elhusseini

Jalal Elhus-Seini

An integrated circuit (IC) includes an adaptive voltage scaling (AVS) controller configured to control a voltage supplied to a portion of the IC and at least one sensor configured to sense at least one state of the IC and to provide an output signal indicative of the at least one sensed state to the AVS controller, the IC having a first setting and a second setting, the AVS controller being configured to use the output signal to control the voltage in the first setting and the AVS controller being configured to control the voltage independently of the output signal in the second setting. Also a method of performing AVS is provided.

Method for performing adaptive voltage scaling (AVS) and integrated circuit configured to perform AVS

The flash and SRAM memory are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce overall power consumption of a mobile telephone employing the ASIC. The flash memory system includes a flash memory array configured to provide a set of individual flash macros and a flash memory controller for accessing the flash macros. The flash memory controller includes a read while writing unit for writing to one of the flash macros while simultaneously reading from another of the flash macros. By permitting read while writing, read operations need not be deferred until completion of pending write operations. The flash memory controller also includes programmable wait state registers. Each wait state register stores a programmable number of flash bus wait states associated with a portion of the flash memory.

Mobile communication device having integrated embedded flash and SRAM memory

The flash and SRAM memory are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce overall power consumption of a mobile telephone employing the ASIC. The flash memory system includes a flash memory array configured to provide a set of individual flash macros and a flash memory controller for accessing the flash macros. The flash memory controller includes a read while writing unit for writing to one of the flash macros while simultaneously reading from another of the flash macros. By permitting read while writing, read operations need not be deferred until completion of pending write operations. The flash memory controller also includes programmable wait state registers. Each wait state register stores a programmable number of flash bus wait states associated with a portion of the flash memory. Thus, portions of flash memory subject to flash memory degradation may be programmed with a higher number of wait states than portions of memory that are not subject to degradation.

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San Diego, CA, United States of America

Stephen Simmonds