Applied Intelligent Systems, Inc.

Environmental Research Institute of Michigan

Other

Kilo, Inc.

Electro Scientific Industries, Inc.

Agro Sciences, Inc.

Stephen S Wilson

Wlodzimierz Holsztynski

William C Steere

Peter M Joseph

The present invention solves the problem of repeated operator intervention in a vision system by providing multiple templates which may be used to locate an object within an image.

Pattern recognition using multiple templates

The present invention relates to a combined approach of image and template correlation, and vector correlation wherein edge detection and pattern searching are joined in a single operation to provide great flexibility without requiring extensive computational facilities. A template is devised from a sparse set of coordinate points that model only the important edges of an object to be located within an image. Different templates are dynamically reconstructed as an estimation of the object location within the image becomes more precise.

Vector correlation system for automatically locating patterns in an image

A method and apparatus is disclosed for converting an interlaced television display to a progressive, scan, or non-interlaced display where artifacts are removed if the source of the signal is from a movie film to television converter, a video recording of a movie, a live camera, or a camera output captured on a video recording system, or any sequence of the above, by utilizing three motion detection stages.

System for deinterlacing television signals from camera video or film

A parallel processing system for processing data matrices, such as images, is disclosed. The system includes a plurality of processing units, organized in four blocks of eight processing units per processing chip, and external cache burst memory, wherein each processing unit is associated with at least one column of the external memory. A barrel shifter connected between the memory and the processing units allows data to be shifted to adjacent processing chips, thus providing the means for connecting several of the chips into a ring structure. Further, digital delay lines are connected between the barrel shifter and the processing units, thus providing the capability of delaying, via a predetermined number of clock cycles, incoming column data. Each processing unit is provided with a nine bit cache memory. The system further includes a controller for each chip that sequences a burst of consecutive rows of a data matrix from the external cache burst memory, to be stored in either the cache memory associated with each of the processing units or routed directly to the processors included in each processing unit. The barrel shifters and the delay lines cooperate to bring horizontally and vertically displaced data points in the external memory to a single processing unit in a single clock cycle period. The controller decodes instructions stored in the external memory, wherein each processing unit receives the same instruction at any given cycle; this decoded instruction is valid for subsequent data bursts from external memory, thus providing the means for allowing instructions and data to be stored in the same external memory without a significant performance penalty. Where the width of an image is greater than the number of processing units, the image must be segmented to be stored in memory. An efficient method of relating column data across segment boundaries is thus provided, using the cache memory of selected processing units.

Cache burst architecture for parallel processing, such as for image

A system and method for floating point computations involving matrices or vectors includes a plurality of identical processing units connected to a linear chain with direct data communication links between adjacent processing units. Each such processor is also connected to its own private memory. A sequence of instructions is sent by a controller to all floating point processing units and their associated memories whereby all processing units in the chain receive the same instruction and all memories receive the same address at any given cycle in the instruction sequence. Each processing unit internally handles floating point operations such as normalization, sign changes, and multiplication in a bit serial manner.

Bit serial floating point parallel processing system and method

A system for processing data matrices such as images and spatially related data includes a plurality of neighborhood processing units connected in a linear chain with direct data communication links between adjacent processing units. A sequence of instructions are sent to the processing units by a single controller, where all neighborhood processing units in the system receive the same instruction at any given cycle in the instruction sequence. The width of the data matrix array is the same as a number of processors, so that there is one processor per column in the data matrix. The memory associated with each processor is external and large enough to hold the entire image or data matrix. The processors are able to operate arithmetically in a serial or parallel mode, where an efficient means is provided to transpose 8.times.8 bit submatrices between the two modes. An indirect addressing means is provided which operates on byte-wide memories external to the processing unit.

Linear chain of parallel processors and method of using same

A system particularly suited for serially processing spatially oriented data such as data matrices includes a plurality of serially connected processing cells for performing a number of successive, different operations on the data using pipeline processing techniques. In one embodiment, each unit cell comprises a memory in the form of a shift register for storing data received from the neighboring, upstream cell. The data is transferred from the memory to a time delaying storage medium such as a latch and to a processing circuit which operates on the data and provides data output to the neighboring, downstream cell. In another embodiment, a simple parallel-in, parallel-out latch is employed as the cell memory thereby allowing the processing circuit to simultaneously access all of the data stored in memory. Data is output from the latch in pre-determined groups and is multiplexed to one portion of the processing circuit. One of the data groups output from the latch is delayed by a shift register and then delivered to another portion of the processing circuit which selectively receives data from the first portion. A central controller connected to each cell controls the transfer of data within and between the cells.

Pipeline processor

An improved method and apparatus for accurately measuring the applied kilovoltage (KV) of an X-ray source over a wide dynamic operating range. A pair of radiation detectors are mounted beneath a rotatable disc having disposed thereon a plurality of metallic absorbers. To measure applied KV, two exposures are required. In the first exposure, called the 'calibration' exposure, the detectors are filtered by two absorbers of equal thickness (t.sub.1) and the detected X-ray intensities are measured, processed, and stored in a digital memory. In the second X-ray exposure, referred to the 'measure' exposure, the filter wheel is automatically advanced so that one detector is filtered by an absorber of thickness (t.sub.1) and the second detector is filtered by an absorber of thickness (t.sub.2). The detected X-rays are gain measured and the ratio of the signals calculated to determine the relative penetrating energy. The data from the second measurement is then modified in accordance with the data from the calibration exposure before applied KV is derived to correct for gain differences in the detectors and associated electronics as well as for any nonuniformities in the radiation striking the detectors. Offset errors and drifts in the electronics are also automatically compensated for.

Method and apparatus for measuring the applied kilovoltage of X-ray

A method and apparatus for automatically analyzing seed characteristics. The seeds are placed one each in associated cells in a tray and the cells are filled with a deionized liquid such as distilled water. After a predetermined period of time, the conductivity of the resultant exudates are measured to provide a visual indication of the seed characteristics such as viability, vigor, and physical damage. In the apparatus, a probe head having a plurality of electrode pairs is placed on the tray so that each electrode pair is immersed in the exudate in each of the cells. An electrical potential is established between each electrode pair and the current flowing therebetween is sequentially scanned to automatically provide a visual indication of the exudate conductivity for each of the seeds in the tray cells. Preferably, the electrodes are first brought to the same potential to stabilize the exudate before establishing the potential difference across the electrodes which creates the current flow.

Seed viability analyzer

A rectangular digital logic array for performing transformations on data matrices for solving wave equations, image processing problems and the like, includes a plurality of identical cells each having a processing element which receives one of its inputs from a single bit accumulator and provides its output to a similar single bit accumulator. The input accumulators of each row in the array are formed by a single parallel input, parallel output shift register and the output accumulators of each column in the array are similarly formed by a parallel input, parallel output shift register. The shift registers operate to connect each cell except those at the edge of the array with two neighboring cells along one axis and two neighboring cells along the orthogonal axis. Four edge shift registers bordering the array allow data to be transferred into and out of the cells and a central processor connected to each of the cells controls the sequence of cell operations and the transfer of data between cells for all cells simultaneously. The simple cell and interconnection structure allows the economical formation of large arrays so that very high processing speeds may be achieved despite the multiple processing steps which each elemental cell must undergo in order to perform a complex computation.

Cellular digital array processor

A transponder/interrogator system for remotely identifying objects. The interrogator emits infrared pulses to activate and remotely clock the transponder. Upon such activation, the transponder emits a unique code in the form of infrared pulses in accordance with a program stored in a recirculating shift register. The interrogator receives the infrared pulses from the transponder and decodes them. The decoded information is then supplied to a controller which runs various status checks on the object identified.

Growing community of inventors

Ann Arbor, MI, United States of America

Stephen S Wilson