Prime Computer Inc.

Encore Computer Corporation

Stephen S Corbin

David J Schanin

Brian Lefsky

Paul K Rodman

Russel L Moore

John Reed Bartlett

Steven J Frank

Charles S Namias

David W Zopf

Mark J Matale

Brian D Gill

David F Ford

Trevor A Creary

Disclosed is a multiprocessor computer system including a plurality of processor modules with each of the processor modules including at least one processor and a cache memory which is shared by all of the processors of each processor module. The processor modules are connected to a system bus which comprises independent data, address, vectored interrupt, and control buses. A system memory which is shared by all the processor modules is also connected to the buses, and the cache memories in each processor module store those memory locations in the main memory most frequently accessed by the processors in its module. A system control module controls the operation and interaction of all of the modules and contains the bus arbiters for the vector, data and address buses. The system control module also controls the retrying of requests which are not completed and should any requester fail to obtain access to a bus, the system control module also unjams this deadlock. Each of these multiprocessor computer systems can be connected to another multiprocessor computer system through an interface which includes a cache for housing frequently accessed locations of the other multiprocessor system.

Multiprocessor computer system employing a plurality of tightly coupled

A memory alignment system and method are disclosed having a memory bus designed to accommodate more than one write instruction at a time and where data from different write instructions are merged together when the writes are destined for alignable locations in memory. In one embodiment, a write buffer and a comparator are configured to compare successive instructions for alignable destination addresses. In another embodiment, a content associative buffer is employed to compare the address of a write instruction with the addresses of all other stored write instructions. A variable scheduler to control the unloading of the buffer is also disclosed as is an apparatus for merging data read from memory with data awaiting transmission to memory to obtain the most up-to-date version.

Memory alignment system and method

Growing community of inventors

Natick, MA, United States of America

Stephen S Corbin