Intel Corporation

Other

Rutgers, the State University of New Jersey

Kabivitrum Ab

Kabi Pharmacia Ab

Corollary, Inc.

Lever Brothers Company

Research, Incorporated

Vitrum Ab

Stephen S Chang

Pete D Vogt

George P White

Yongde Bao

Nagabhushan Chitlur

Chi-Tang Ho

Timothy J Pelura

Kejian J Wu

Pratik M Marolia

Michael C Adler

Brian R Bennett

Nishit Patel

Sreedhar Ravipalli

Teng Wang

Jonathan Lo

Michael T Werstlein

An-Li Hsieh

Cheng-Li Huang

Lars Lindmark

Barbara A Izzo

Christopher M Houlihan

Rohan Menezes

Mariano Aguirre

Biserka Ostric-Matijasevic

Michael Werstlein

A server having a host processor coupled to a programmable coprocessor is provided. One or more virtual machines may run on the host processor. The coprocessor may be coupled to an auxiliary memory that stores virtual machine (VM) states. During live migration, the coprocessor may determine when to move the VM states from the auxiliary memory to a remote server node. The coprocessor may include a coherent protocol home agent and state tracking circuitry configured to track data modification at a cache line granularity. Whenever a particular cache line has been modified, only the data associated with that cache line will be moved to the remote server without having to copy over the entire page, thereby substantially reducing the amount of data that needs to be transferred during migration events.

Methods and apparatus for accelerating virtual machine migration

In connection with an access of content from a cache, a snoop request can be sent to one or more remote cache devices to determine if any other cache has a copy of the content. A link between the cache and the remote cache devices can include a snoop bypass device. The snoop bypass device can monitor content cached by the one or more remote devices on a cache line or coarser granularity. The snoop bypass device can respond to the snoop request with a negative indication based on a coarser granularity tracking of content of the one or more remote cache devices.

Management of cache use requests sent to remote cache devices

There is disclosed in one example an accelerator apparatus, including: a programmable region capable of being programmed to provide an accelerator function unit (AFU); and a platform interface layer (PIL) to communicatively couple to the AFU via an intra-accelerator protocol, and to provide multiplexed communication with a processor via a plurality of platform interconnect interfaces, wherein the PIL is to provide abstracted communication services for the AFU to communicate with the processor.

Platform interface layer and protocol for accelerators

A method and apparatus for dynamically modifying routing information in an interconnect architecture without quiescence is herein described. Each agent/node holds routing information regarding target agents/nodes in an interconnect architecture, which may include routing preferences. When a node is to be hot removed, it generates port disable messages to neighbors. The neighbors disable a port the disable message is received on and generates a completion message back to the not to be removed. The node to be removed continues to route messages until it receives a completion; at which time it disables a corresponding node. When all nodes are disabled the device may be removed. Other nodes in the interconnect architecture learn of an agent removal through use of return cycles when messages reach dead ends during attempted routing of cycles. Furthermore, hot addition of a node includes broadcasting of an enable message to enable nodes for routing to the added node.

Dynamic update of route table

Some embodiments of the invention include a method of preventing live-lock in a multiprocessor system. The method comprising identifying a first bus transaction attempting to modify a resource and setting a status bit to indicate that a bus transaction attempting to modify the shared resource is pending. The method further comprising retrying each subsequent nonmodifying bus transaction for the shared resource until the status bit is cleared.

Prevention of live-lock in a multi-processor system

An embodiment of the present invention includes a task table to store a task entry corresponding to a first task associated with a first processor. A snoop controller controls snooping an access reference to a cache line in a task block in response to a second task cycle generated by a second processor according to a snoop condition.

Controlling snoop activities using task table in multiprocessor system

An embodiment of the present invention is a task manager to manage tasks in a multiprocessor system. A task table stores task entries corresponding to tasks executed by at least one processor. A block allocation circuit allocates blocks of the cache memory used by the tasks. A task coordinator coordinates the tasks in response to a task cycle issued by a processor.

Task-based multiprocessing system

A first circuit is to generate a data signal containing data. A second circuit is to utilize said data, where the first and second circuits are commonly clocked by a latch signal, further a circuit has a first level sensitive latch to latch the data signal from the first circuit upon receiving by way of a delay circuit the latch signal, and a second level sensitive latch to latch an output signal of the first level sensitive latch to the second circuit upon receiving the latch signal. Other embodiments are also described and claimed.

Method and apparatus to delay signal latching

Cache states for cache coherency protocols for a multiprocessor system are described. Some embodiments described include a multiprocessor computer system comprising a plurality of cache memories to store a plurality of cache lines and state information for each one of the cache lines. The state information comprises data representing a first state selected from the group consisting of a Shared-Update state, a Shared-Respond state and an Exclusive-Respond state. The multiprocessor computer system further comprises a plurality of processors with at least one cache memory associated with each one of the plurality of processors. The multiprocessor computer system further comprises a system memory shared by the plurality of processors, and at least one bus interconnecting the system memory with the plurality of cache memories and the multiple processors. In some embodiments, one or more of the states (a Shared-Update state, a Shared-Respond state or an Exclusive-Respond state) are implemented in conjunction with the states of the MESI protocol.

Cache states for multiprocessor cache coherency protocols

An apparatus includes a first latch having an output terminal. A latch signal is received by the first latch. A second receives the latch signal and having an input terminal coupled to the output terminal of the first latch. A delay circuit delays the latch signal to the first latch.

A cache-coherent, multiple-bus, multiprocessing system and method interconnects multiple system buses and an I/O bus to a shared main memory and efficiently maintains cache coherency while minimizing the impact to latency and total bandwidth within the system. The system provides coherency filters which coordinate bus-to-bus communications in such a way as to maintain cache memory coherency with a small amount of cross-bus traffic. In addition, the system provides a multiported pool of memory cells which interconnect the multiple buses.

System and method for maintaining memory coherency in a computer system having multiple system buses

System and method for maintaining memory coherency in a computer system

Growing community of inventors

Glendora, CA, United States of America

Stephen S Chang