Synopsys, Inc.

Conductus, Inc.

Stephen Robert Whiteley

Jamil Kawa

Victor Moroz

Eric M Mlinar

Robert E Freeman

Eby G Friedman

Rang-Chen Yu

Barry Hugh Whalen

Abdelrahman G Qoutb

A superconducting anti-fuse based field programmable gate array (FPGA) may include a first set of superconducting passive transmission lines, a second set of superconducting passive transmission lines, and at least one anti-fuse located at an intersection of a first superconducting passive transmission line from the first set of superconducting passive transmission lines and a second superconducting passive transmission line from the second set of superconducting passive transmission lines. A first terminal of the anti-fuse may be electrically connected to the first superconducting passive transmission line and a second terminal of the anti-fuse may be electrically connected to the second superconducting passive transmission line. The anti-fuse may transition from a first state having a non-zero resistance to a second state having a zero resistance below a critical temperature.

Superconducting anti-fuse based field programmable gate array

A structure may include a set of metal layers disposed on a substrate layer, where a dielectric material is disposed between adjacent metal layers in the set of metal layers. The structure may include a first superconducting structure and a second superconducting structure created in a metal layer selected from the set of metal layers. The first superconducting structure may have a first length along a first direction which is parallel to a primary routing direction of the metal layer, a second length along a second direction which is parallel to the substrate layer and perpendicular to the first direction, and a third length along a third direction which is directed away from the substrate layer and perpendicular to the first direction and the second direction. The third length may be greater than the second length.

Interconnects, inductors, transformers, and power architectures for circuits

On-chip testing of a superconductive integrated circuit device includes receiving a superconductive circuit design having superconductive logic elements. Further, a first testability characteristic for first test circuitry at a first node within the superconductive circuit design is determined. The first testability characteristic corresponds to one or more of a test generation control level and a test observability control level. An updated superconductive circuit design from the superconductive circuit design is generated based on the first testability characteristic for the first test circuitry. The superconductive circuit design includes the first test circuitry at the first node.

Superconductive integrated circuit devices with on-chip testing

Josephson junction (JJ) structures are disclosed. In some embodiments, a JJ structure may include alternating planar superconducting structures and planar non-superconducting structures arranged along a direction away from a wafer surface.

Josephson junction structures

A parameterized superconducting circuit may include a set of sub-blocks which include superconducting circuitry. Different sub-blocks in the set of sub-blocks may be clocked using clock signals having different phases. Along a first direction, relative locations of the set of sub-blocks may be fixed. Along a second direction, relative locations of the set of sub-blocks may be determined based on a set of parameter values.

Parameterized superconducting multi-row circuit

Disclosed herein are embodiments including electrical structures that includes a first cell, a first inductor, a first resistor, and a first shunted Josephson junction. The first inductor is connected in series with the first shunted Josephson junction at a first terminal end of the first inductor and a second terminal end of the first inductor is connected to a feed point of the first cell being powered. A first end of the first resistor having connected to ground and a second end being connected to the first shunted Josephson junction at a terminal of the first shunted Josephson junction that is not connected to the first inductor. A source of an electrical current source that is external to the first cell is connected to the first shunted junction and the first resistor at a common point.

Energy-efficient SFQ logic biasing technique

The present disclosure relates to improved electronic structures for propagating logic states between superconducting digital logic gates using a three-junction interferometer in a receiver circuit to reduce reflecting signals that otherwise result in distortions in the signals being transmitted between the gates. Other improved electronic structures comprise passive transmission lines (PTLs) with transmission line matching circuitry that has previously been avoided. The matching circuitry minimizes generation and propagation of spurious pulses emitted by Josephson junctions used in the digital logic gates.

Interference reducing passive transmission line receiver

A circuit can include a first sub-circuit, a second sub-circuit, and a third sub-circuit. The first sub-circuit can store a reset state or a set state, and can include a first Josephson junction (JJ), a second JJ, and a third JJ coupled in parallel using superconducting inductors. The first JJ, the second JJ, and the third JJ can be biased using a JJ-based current source. The second sub-circuit can switch the first sub-circuit to the set state in response to receiving a pulse. The third sub-circuit can switch the first sub-circuit to the reset state in response to receiving one or more pulses.

Single flux quantum inverter circuit

Josephson junction (JJ) structures are disclosed. In some embodiments, a JJ structure may include a first superconducting structure and a second superconducting structure disposed on a plane parallel to a silicon wafer surface. A non-superconducting structure may be disposed between the first superconducting structure and the second superconducting structure. A direction of current flow through the non-superconducting structure may be parallel to the silicon wafer surface.

The independent claims of this patent signify a concise description of embodiments. Disclosed is technology for direct measurement of the capacitance of a Josephson junction. Roughly, the technique includes detecting the resonance frequency f of the junction under test, determining the DC voltage Vp across the junction under test at resonance frequency, and determining the capacitance of the junction under test in dependence upon the critical current Ic of the junction under test and the DC voltage Vp. This Abstract is not intended to limit the scope of the claims.

Direct measurement of Josephson junction capacitance

A single flux quantum (SFQ) cell may include SFQ circuitry to implement a logic function that generates logic values of a set of outputs based on logic values of a set of inputs. The SFQ circuitry may instantaneously update logic values of the set of outputs in response to changes in logic values of the set of inputs. The SFQ circuitry may include at least one SFQ non-destructive set-reset flip-flop.

Complementary asynchronous single flux quantum circuits

Josephson junction (JJ) structures are disclosed. In some embodiments, a JJ structure may include a non-superconducting structure having a hollow region. A first superconducting structure may be disposed inside the hollow region of the non-superconducting structure, and a second superconducting structure may be disposed around the non-superconducting structure outside the hollow region.

A circuit can include a first Josephson junction (JJ), a second JJ, and a third JJ coupled in parallel using superconducting inductors. The first JJ, the second JJ, and the third JJ can be biased using one or more JJ-based current sources.

Single flux quantum buffer circuit

A single flux quantum (SFQ) circuit can include a combinational logic network, which can include a set of SFQ logic cells. The SFQ circuit can also include an SFQ sequencing circuit, which can be used to generate delayed versions of clock pulses to clock the set of SFQ logic cells.

Single flux quantum circuit that includes a sequencing circuit

An apparatus and method for obtaining ultra-high speed operation of a semiconductor laser diode is presented. The invention utilizes any of a variety of conventional laser diodes in combination with cooling means for operation of the laser at temperatures below 120 K. Input electrical signals may include signals on a 28 GHz signal carrier and pulsed signals. An extended fiber optics cable may be used to operate the system as an optical delay line.

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Sunnyvale, CA, United States of America

Stephen Robert Whiteley