Qualcomm Incorporated

Stephen Robert Shannon

Suresh Kumar Venkumahanti

Lin Wang

Lucian Codrescu

Phillip M Jones

Robert Allan Lester

Jiajin Tu

Karan Suri

Puneet Talwar

Daisy T Palal

Sharing loop cache instances among multiple threads in processor devices is disclosed herein. In some aspects, a processor device provides a loop cache controller circuit that is configured to detect a first iteration of a loop body, comprising a plurality of loop instructions, in an instruction stream executed by a first thread. The loop cache controller circuit determines that the loop instructions were previously stored in a loop cache instance associated with a second thread, and, in response, sets a use bit corresponding to the first thread of a use bit register corresponding to the loop cache instance. Upon detecting a subsequent iteration of the loop body by the first thread, the loop cache controller circuit retrieves the plurality of loop instructions from the loop cache instance instead of an instruction cache, based on the use bit corresponding to the first thread.

Sharing loop cache instances among multiple threads in processor devices

Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.

Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer-readable media

An apparatus includes an access mode selection circuit configured to select a cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit coupled to a cache, or both. The access mode selection circuit is further configured to generate an access mode signal based on the selected cache access mode. The apparatus further includes an address generation circuit configured to perform a cache access based on the access mode signal.

Reconfigurable fetch pipeline

A particular method includes selecting between a first cache access mode and a second cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit, or both. The method further includes performing a first cache access. When the first cache access mode is selected, performing the first cache access includes performing a tag access and performing a data array access after performing the tag access. When the second cache access mode is selected, performing the first cache access includes performing the tag access in parallel with the data array access.

Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes.

Growing community of inventors

Austin, TX, United States of America

Stephen Robert Shannon