Analog Devices,inc.

Stephen Robert Kosic

Corey Petersen

Jeffrey Paul Bray

Janet M Brunsilius

Lawrence A Singer

Steven J Decker

Eric John Siragusa

Daniel F Kelly

Efram Burlingame

A circuit can include an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, a circuit node, and a connection element connecting the n-well to the circuit node. The connection element can include a diode having an anode terminal connected to the circuit node and a cathode terminal connected to the n-well, a resistor having a first terminal connected to the circuit node and a second terminal connected to the n-well, a conductor directly connecting the n-well to the circuit node, or a well switch configured to connect the n-well to the circuit node during an enable phase of a switching signal and to electrically float the n-well during a non-enable phase of the switching signal. The diode can include a diode-connected transistor. The circuit node can be configured to receive a predetermined voltage having a magnitude equal to or greater than an upper supply voltage.

Dynamically driven deep n-well circuit

A system, method, and computer program product for generating a regulated boosted load voltage. A comparator may use reduced versions of a reference voltage, a supply voltage, and a fed-back output load voltage to determine whether the output load voltage requires adjustment. If so, a controller may responsively vary the number of voltage boosting charge pumps connected in parallel to the load to best match a target voltage. The target voltage may be the reference voltage plus the supply voltage. A counter may track the number of active charge pumps, and may increment or decrement the number more slowly than the charge pumps operate. Loop gain may be limited by an integrating filter to prevent oscillation. The embodiments are of particular utility for signal conversion circuitry as they eliminate difficulties arising from gate-source voltage inadequacies and differences in switch transistors. A wider range of reference voltages may be accommodated.

System and method for generating a regulated boosted voltage using a controlled variable number of charge pump circuits

A method and a device for canceling an offset voltage in an output of a comparator circuit include applying a signal to a first input of the comparator as a function of an initial tap point in a resistor ladder. While the signal is applied to the first input, a nominal voltage is applied to a second input of the comparator, and then an output of the comparator is analyzed. The signal to the first input is changed in response to the analyzing, by accessing a different tap point in the resistor ladder.

Foreground techniques for comparator calibration

A method and a corresponding device for performing a background calibration of a comparator in a circuit having a plurality of stages that are connected in a pipelined fashion to an input signal. A digital value of a residue signal, which is output from a first stage in the plurality of stages to a subsequent stage in the plurality of stages, is calculated. The value of the residue signal is compared to at least one threshold. Based on the comparison, a triggering threshold of a selected comparator in the first stage may be adjusted.

Background techniques for comparator calibration

A switched-capacitor digital-to-analog converter (DAC) circuit can include first and second sets of capacitors, an amplifier, a reference signal generator and interconnecting switches. The first and second sets of capacitors can be connected to first and second analog input signals responsive to a first clock signal, and to first and second reference voltages responsive to a second clock signal and digital control signals. The amplifier can be connected to the first and second sets of capacitors in response to the second clock signal. The reference signal generator can provide to the first and second sets of capacitors, responsive to the first clock signal, a common-mode reference signal to set a common-mode voltage at inputs of the amplifier, and can include components to replicate the operation of the first and second sets of capacitors. The switched-capacitor DAC circuit can be used to implement a multiplying DAC in a pipeline analog-to-digital converter.

Switched-capacitor MDAC with common-mode hop regulation

A method and a device for canceling an offset voltage in an output of a comparator circuit include sampling a set of offset voltages; applying a set of correction voltages equal in magnitude and opposite in polarity to the set of offset voltages, the set of correction voltages being applied to an output generating arrangement of the comparator circuit; and enabling output of the output generating arrangement after the set of correction voltages is applied.

Method and device for comparator offset cancellation

A circuit includes an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, and a first well switch configured to selectively connect the n-well to a predetermined voltage in response to an enable phase of a first switching signal. The first well switch can be configured to connect the n-well to the predetermined voltage during the enable phase of the first switching signal and to electrically float the n-well during a non-enable phase of the first switching signal.

Dynamically-driven deep n-well circuit

A differential two-stage Miller compensated amplifier system with capacitive level shifting includes a first stage differential transconductance amplifier including first and second output nodes and an output common mode voltage, a second stage differential transconductance amplifier including non-inverting and inverting inputs and outputs and an input common mode voltage, and a level shifting capacitor circuit coupled between the first and second output nodes and the non-inverting and inverting inputs for level shifting between the output common mode voltage of the first stage and the input common mode voltage of the second stage.

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San Diego, CA, United States of America

Stephen Robert Kosic