Intel Corporation

Stephen R Van Doren

Rajesh M Sankaran

Ishwar Agarwal

Yen-Cheng Liu

Niall D McDonnell

Gilbert A Neiger

David A Koufaty

Rupin H Vakharwala

Joseph Nuzman

Christopher J Hughes

Andrew J Herdrich

Samantika S Sury

Doddaballapur N Jayasimha

Jonas Svennebring

Robert Valentine

Mark Jay Charney

Jesus Corbal

Tsung-Yuan Charles Tai

Edward Thomas Grochowski

Mahesh U Wagh

Eriko Nurvitadhi

Koichi Yamada

Thomas D Fletcher

Deborah T Marr

Paul Caprioli

Lokpraveen B Mosur

Narayan Ranganathan

Dennis Ryan Bradford

Kent D Glossop

Jonathan D Pearce

Richard J Greco

Jeffrey J Cook

Ganesh Venkatesh

Asit K Mishra

Ramacharan Sundararaman

Mark S Myers

Dwight P Manley

Tracy Garrett Drysdale

David B Sheffield

Nicholas P Carter

David M Durham

David J Harriman

Ren Wang

Uday R Savagaonkar

Prashant Dewan

Carlos V Rozas

Francis X Mckeen

Vincent R Scarlata

Debra Bernstein

John I Garney

Jr-Shian Tsai

Ernie F Brickell

Simon P Johnson

David Sonnier

Howard C Herbert

Gary L Graunke

Dion Rodgers

Michael A Goldsmith

Stalinselvaraj Jeyasingh

William G Burroughs

Edwin Verplanke

Hugh Wilkinson

Pratik M Marolia

Jeffrey D Chamberlain

Yipeng Wang

Joseph Frank Cihula

Andrew Cunningham

Bruce Richardson

James T Clee

Narender R Vangati

Debendra Das Sharma

Aravindh V Anantaraman

Ashok Raj

Bahaa Fahim

Bradley A Burres

Michelle C Jen

Dimitrios Ziakas

Bassam N Coury

Andreas Kleen

Namakkal N Venkatesan

Stephen J Robinson

Amin Firoozshahian

Mahesh Srinivasa Maddury

Omid Azizi

Vedvyas Shanbhogue

Siddhartha Chhabra

Hormuzd M Khosravi

Wei P Chen

Robert G Blankenship

Barry E Huntley

Ravishankar Iyer

Mark A Schmisseur

Raghunandan Makaram

Stephen T Palermo

Vedaraman Geetha

Chandan Egbert

Julius Yuli Mandelblat

Larisa Novakovsky

Amy L Santoni

Adrian C Moga

Techniques and mechanisms to facilitate access to a cache based on a dual basis partition scheme. In an embodiment, a first one or more registers of a processor provide information which describes multiple set-wise partitions of a cache. A second one or more registers of the processor provides additional information which describes multiple way-wise partitions of the cache. A virtual cache is defined as that region of the cache which is both in a particular set-wise partition, and in a particular way-wise partition. In another embodiment, a cache agent of the processor performs operations, based on the set-wise partitioning and the way-wise partitioning, to determine a mapping of one address—which is provided in a memory access request, and which indicates a location in one virtual cache—to another address which indicates another location in a different virtual cache.

Two-stage cache partitioning

Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

Non-posted write transactions for a computer bus

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Systems, methods, and apparatuses for heterogeneous computing

Embodiments may be generally direct to apparatuses, systems, method, and techniques to detect a message to communicate via an interconnect coupled with a device capable of communication via a plurality of interconnect protocols, the plurality of interconnect protocols comprising a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol. Embodiments also include determining an interconnect protocol of the plurality of interconnect protocols to communicate the message via the interconnect based on the message, and providing the message to a multi-protocol multiplexer coupled with the interconnect, the multi-protocol multiplexer to communicate the message utilizing the interconnect protocol via the interconnect with the device.

Techniques to support mulitple interconnect protocols for an interconnect

Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization processes prior to receiving one or more data packets that rely on memory transactions. The systems and methods can include receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.

Method, apparatus, system for early page granular hints from a PCIe device

Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

Techniques to support multiple protocols between computer system interconnects

A fabric controller to provide a coherent accelerator fabric, including: a host interconnect to communicatively couple to a host device; a memory interconnect to communicatively couple to an accelerator memory; an accelerator interconnect to communicatively couple to an accelerator having a last-level cache (LLC); and an LLC controller configured to provide a bias check for memory access operations.

Bias-based coherency in an interconnect fabric

Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.

Remote atomic operations in multi-socket systems

Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.

Spatial and temporal merging of remote atomic operations

An integrated circuit includes a core and memory controller coupled to a last level cache (LLC). A first key identifier for a first program is associated with physical addresses of memory that store data of the first program. To flush and invalidate cache lines associated with the first key identifier, the core is to execute an instruction (having the first key identifier) to generate a transaction with the first key identifier. In response to the transaction, a cache controller of the LLC is to: identify matching entries in the LLC by comparison of first key identifier with at least part of an address tag of a plurality of entries in a tag storage structure of the LLC, the matching entries associated with cache lines of the LLC; write back, to the memory, data stored in the cache lines; and mark the matching entries of the tag storage structure as invalid.

Write-back invalidate by key identifier

A fabric controller is provided for a coherent accelerator fabric. The coherent accelerator fabric includes a host interconnect, a memory interconnect, and an accelerator interconnect. The host interconnect communicatively couples to a host device. The memory interconnect communicatively couples to an accelerator memory. The accelerator interconnect communicatively couples to an accelerator having a last-level cache (LLC). An LLC controller is provided that is configured to provide a bias check for memory access operations on the fabric.

Coherent accelerator fabric controller

Growing community of inventors

Portland, OR, United States of America

Stephen R Van Doren