Conner Peripherals, Inc.

Texas Instruments Corporation

Intersect Technologies, Inc.

Maxtor Corporation

Stephen R Cornaby

Tracy D Harmer

Lance R Carlson

Scott E Burton

An arrangement and method are disclosed herein for operating a mass memory storage peripheral computer device connected to a host computer. The host computer has system RAM associated with the host computer and is operated using an operating system and a system BIOS. The mass memory storage peripheral computer device is connected to the host computer using a peripheral bus in which relocatable expansion BIOS location addresses are allowed. The arrangement and method include a loadable device driver for controlling the operation of the mass memory storage peripheral computer device during the operation of the computer system. During the start-up of the computer system, the loadable device driver is loaded into the system RAM for use during the operation of the system. The loadable device driver allows the host computer to communicate with and control the operation of the mass memory storage peripheral computer device in a way which does not require the system BIOS or any other type of protocol translation mechanism to be provided between the loadable device driver and the operating system or the mass memory storage peripheral computer device in order for the loadable device driver to communicate with the operating system and the mass memory storage peripheral computer device.

Method and arrangement for operating a mass memory storage peripheral computer device connected to a host computer

A computer controlled system includes a data storage device connected to a host computer using a bus which allows device-initiated bus-mastering. The system has system RAM which is associated with the host computer and which is not part of the data storage device. The data storage device requires certain device operating data/code in the form of device control means and device operating data to be used to control the operation of the device. An arrangement and method for operating the data storage device includes storing at least a portion of the device operating data/code in the system RAM. The arrangement and method further include allowing the host computer and/or the data storage device access to the device operating data/code stored in the system RAM such that the host computer and/or the data storage device may use the device operating data/code to control the operation of the data storage device.

Method and arrangement for allowing a computer to communicate with a data storage device

Method and arrangement for allowing a computer to communicate with a

The present invention provides a method and apparatus for assuring that the desired data is transferred between a variable rate disk drive and a host system during read and write operations. The invention involves retaining a variable amount of data in a buffer memory after the data has been transferred between the buffer memory and a magnetic disk with the variable amount of data retained based upon a predetermined fixed period of time associated with error conditions and a disk transfer rate. If an error condition is detected during a transfer of data between the buffer memory and the disk, all of the retained data may be retransferred after the error condition has been corrected.

Time based data retention in a variable data rate disk drive

A plurality of queues where each queue is defined by a set of criteria, the queue system comprises a plurality of header registers where each header register defines a queue in the queue system and a plurality of task registers where each task register can be associated with each queue in the queue system. Each header register has a unique address and contains a previous field and a next field. Each task register has a unique address and contains a previous field and a next field. Each previous field and said next field stores the address of another register in a given queue such that each queue is formed in a double link structure. Control means is provided for dynamically assigning task registers to queues by controlling the addresses stored in the previous and next fields in each header and task registers such that each of said task registers is always assigned to a queue in the queue system.

Queue system for dynamically allocating and moving memory registers

A serial data transmission system employing at least three transmission lines for transmitting the serial data. Each of the transmission lines can be designated as a data line 1 or as a data line 2. An encoder dynamically designates, for each binary data bit transmission period, one transmission line as data line 1 and one transmission line as data line 2 such that the transitions representing two data bits being transmitted in two successive transmission periods not occur on any one of the transmission lines. In each binary data bit transmission period, the encoder will cause a transition to occur on either data line 1 or data line 2 as a function of the value of the data bit to be transmitted during that transmission period. A decoder retrieves the data bit for each transmission period in accordance with whether the transition occurred on the transmission line designated as data line 1 or the transmission line designated as data line 2 for that period and determines for the next transmission period which of the transmission lines will be designated as the data line 1 and which of the transmission lines will be designated as the data line 2.

Data transfer system

A task assigning system within a dual actuator disk drive system wherein each task has a cylinder address comprising a plurality of registers, each register having a unique address and a plurality of fields for storing a task including the cylinder address associated with the tasks, a queue comprising a header register, the header register having a plurality of fields, an insertion means for inserting and ordering the registers into the queue when a task is first stored into the register, a first means for assigning tasks stored in the queue to a first actuator of the dual actuators in the sequence of increasing value of the cylinder addresses of tasks stored in the registers in the queue and a second means for assigning tasks stored in the queue to a second actuator of the dual actuators in the sequence of decreasing values of the cylinder addresses of the tasks stored in the registers in the queue.

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Niwot, CO, United States of America

Stephen R Cornaby