Terarecon, Inc.

Stephen R Burgess

Hanspeter Pfister

Hugh C Lauer

James M Knittel

Takahide Ohkami

Christopher J Kappler

Jan C Hardenbergh

William R Peet

Kenneth W Correll

Jay C Wilkinson

Stephen F Mason

Beverly J Schultz

A plurality of identical rendering pipelines are connected in parallel to read an array of voxels and to write an array of pixels. Each pipeline processes one voxel in one processing cycle of the pipelines. Each pipeline includes a plurality of serially connected different stages. The stages can include interpolation, classification, gradient estimation, illumination, and compositing stages. Interfaces connect identical stages in adjacent pipelines as one-way rings to communicate information associated with spatially adjacent voxels, and delay buffers connected parallel to particular stages communicate information associated with temporally adjacent voxels.

Volume rendering pipeline

A volume rendering integrated circuit includes a plurality of interconnected pipelines having stages operating in parallel. The stages of the pipelines are interconnected in a ring, with data being passed in only one direction around the ring. The volume integrated circuit also includes a render controller for controlling the flow of volume data to and from the pipelines and for controlling rendering operations of the pipelines. The integrated circuit may further include interfaces for coupling the integrated circuit to various storage devices and to a host computer.

Volume rendering integrated circuit

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Medfield, MA, United States of America

Stephen R Burgess