Coventor, Inc.

Stephen R Breit

David M Fried

Kenneth B Greiner

Daniel Faken

Mattan Kamon

Gunar Lorenz

Mark J Stock

A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology measurement data from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.

System and method for predictive 3-D virtual fabrication

A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.

System and method for performing a multi-etch process using material-specific behavioral parameters in a 3-D virtual fabrication environment

Predictive 3-D virtual fabrication system and method

A virtual fabrication environment for semiconductor device structure development is discussed that enables the use of a selective epitaxy process to virtually model epitaxial growth of a crystalline material layer. The epitaxial growth occurs on a crystalline substrate surface of a virtually fabricated model device structure. A surface growth rate may be defined over possible 3D surface orientations of the virtually fabricated device structure by modeling the growth rates of the three major families of crystal planes. Growth rates along neighboring non-crystalline material may also be modeled.

System and method for modeling epitaxial growth in a 3-D virtual fabrication environment

A virtual fabrication environment for semiconductor device structure development is discussed. The insertion of a multi-etch process step using material-specific behavioral parameters into a process sequence enables a multi-physics, multi-material etching process to be simulated using a suitable numerical technique. The multi-etch process step accurately and realistically captures a wide range of etch behavior and geometry to provide in a virtual fabrication system a semi-physical approach to modeling multi-material etches based on a small set of input parameters that characterize the etch behavior.

Multi-etch process using material-specific behavioral parameters in 3-D virtual fabrication environment

A virtual fabrication environment that enables 3D Design Rule Checks (DRCs) or Optical Rule Checks (ORCs) on 3D structural models of semiconductor devices to be performed is discussed. The virtual fabrication environment may perform 3D design rule checks, such as minimum line width, minimum space between features, and minimum contact area between adjacent materials, directly in 3D without making assumptions about the translation from 2D design data to a 3D structure effected by an integrated process flow for semiconductor devices. The required number of 3D design rule checks may therefore be significantly reduced from the number of design rule checks required in 2D environments. Embodiments may also perform the 3D design rule checks for a range of statistical variations in process and design parameters.

Rule checks in 3-D virtual fabrication environment

A system-level design and simulation environment utilizing a process specification tool that is programmatically integrated with the system level design and simulation environment thereby enabling the process-flexible design and simulation of Micro Electro-Mechanical Systems (MEMS) devices and other micro-fabricated devices is disclosed. The process specification tool is a software tool for specifying the details of the fabrication process and enables the separation of the process data from the system-level design and simulation environment. The process specification tool retrieves the process data, which may include both the process specification and material properties data. The separation of this process data from the system-level design and simulation environment allows the system-level model to have process-related parameters whose specification is not fixed, but rather is tied by reference to the process data. The tying of components to the process data allows the system-level environment to extract multiple process parameters for each component model instead of requiring duplicate entry of these parameters in each component model, a time-consuming and error prone process. Modifications of the process data are programmatically communicated to the system-level environment. The dynamic response to changes in the process data allows alternative simulations to be run more effectively and quickly than in traditional IC design environments.

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Wayland, MA, United States of America

Stephen R Breit