International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

Stephen Peter Ayotte

Timothy M Sullivan

Glen E Richard

David J Hill

Timothy Dooling Sullivan

Jeffrey P Gambino

Adam J McPadden

Shawn Peter Fetterolf

Heather M Truax

Timothy Harrison Daubenspeck

Wolfgang Sauter

Christopher David Muzzy

Eric Gerhard Liniger

Kimball M Watson

John Thomas Kinnear, Jr

Michael Russell Uy Gonzales

Nicholas G Clore

Travis S Longenbach

Christina Marie Pepi

Benjamin J Pierce

Mark Tiam Weng Lam

Kristen L Holverson

Hanyi Ding

David Lewis Gardell

Jeffrey D Gilbert

John Chester Malinowski

Ronald Lee Mendelson

Jared P Yanofsky

Andrew H Norfleet

Mark T W Lam

Kendra A Lyons

Alissa R Cote

Michael C Johnson

Sebastien S Quesnel

Sebastien Quesnel

Petra U Klinger-Park

Marvin G L Montaque

Sanda S Myat

A contactless readable programmable transponder to monitor chip join and method of use are disclosed. The method includes reading a frequency of an oscillator associated with a chip module. The method further includes correlating the frequency with a bond quality of the chip module.

Contactless readable programmable transponder to monitor chip join

Quality control testing for a batch of electronic modules. A series of tests are performed on manufactured electronic modules, including tests sensitive to the failure rate of previously tested modules. Specifically, a first test comprised of two phases is performed on the module batch. Further screening is then performed responsive to detection of a wire sweep failure in a subset of failed modules from the first test phase. The further screening is on modules that passed the first test phase and excludes modules that failed the first test phase.

Screening methodology to eliminate wire sweep in bond and assembly module packaging

A system and method for disassembling a multiple contact probe head including a plurality of contact probes positioned by a first die at a first end of the plurality of probes and a second die at a second end of the plurality of probes, are provided. The system may include a manifold configured to sealingly receive an opposing side of the first die from the second die; and a vacuum source operatively coupled to the manifold to apply a vacuum to an interior of the manifold applying a force to the plurality of contact probes in position in the first die across. Where the probes include a paramagnetic material, a magnetic source may be employed to hold the probes during disassembly.

Multiple contact probe head disassembly method and system

A method for predicting the electrical functionality of a semiconductor package, the method includes performing a first stiffness test for a first semiconductor package, receiving failure data for the first semiconductor package, the failure data includes results of an electrical test performed after the first semiconductor package is assembled on a printed circuit board, generating a database comprising results of the first stiffness test as a function of the failure data for the first semiconductor package, performing a second stiffness test for a second semiconductor package, identifying a unique result from the results of the first stiffness test in the database, the unique result aligns with a result of the second stiffness test, and predicting a failure data for the second semiconductor package based on the failure data for the first semiconductor package which corresponds to the unique result of the first stiffness test identified in the database.

Predicting semiconductor package warpage

Embodiments of the present disclosure relate to separating an integrated circuit (IC) structure from an adjacent chip. An IC structure according to embodiments of the disclosure may include: a semiconductor region including an interconnect pad positioned thereon, the interconnect pad electrically connected to a solder bump; and an ohmic heating wire positioned within the semiconductor region and in thermal communication with the interconnect pad, wherein the ohmic heating wire is configured to be heated above a melting temperature of the solder bump.

Separation of integrated circuit structure from adjacent chip

Methods and apparatus for joining a chip with a substrate. The chip is moved by with a pick-and-place machine from a first location to a second location proximate to the substrate over a first time. In response to moving the chip in a motion path from the first location to the second location, a plurality of solder bumps carried on the chip are liquefied over a second time that is less than the first time. While the solder bumps are liquefied, the chip is placed by the pick-and-place machine onto the substrate.

Chip joining by induction heating

Disclosed are processes and apparatuses for semiconductor die removal and rework, including thin dies. In one aspect the process involves the use of a localized induction heating system to melt targeted solder joints, thereby minimizing the degradation of the thermal performance of the assembly undergoing the rework. Use of a vacuum-based die removal head, optionally in combination with the induction heating system, allows for the removal of thin dies of 150 micrometers thick or less.

Method for semiconductor die removal rework

Methods and structures provide an electrostatic discharge (ESD) indicator including an electric field sensitive material configured to undergo a specific color change in response to an electric field. An exposure of the structure to an ESD can be visually determined via the specific color change of the ESD indicator.

Visually detecting electrostatic discharge events

A semiconductor structure in the form of a die comprises a silicon-containing core having a first surface, an opposite second surface and a peripheral edge surface. A circuit structure on the first surface is circumscribed by a peripheral crackstop structure which stops short of the second surface, thereby leaving an accessible portion of the peripheral edge surface free of the crackstop structure. One or more angular or orthogonal edge connector through-silicon conductive vias ('edge connector TSVs') connect the circuit structure to the accessible portion of the peripheral edge surface without penetrating the crackstop structure. A method of making the structure includes forming the edge connector TSVs in the silicon wafer from which the semiconductor structures, i.e., dies, are cut.

Semiconductor structure and method of making

In an approach to determining reliability test strategy, one or more computer processors receive a volume forecast for manufacturing one or more products. The one or more computer processors receive information describing the one or more products. The one or more computer processors retrieve reliability test requirements associated with the one or more products. The one or more computer processors retrieve reliability test capability of one or more reliability test vendors. The one or more computer processors determine, based, at least in part, on the volume forecast, the information describing the one or more products, the reliability test requirements, and the reliability test capability of the one or more reliability test vendors, a reliability test strategy.

Reliability monitor test strategy definition

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Bristol, VT, United States of America

Stephen Peter Ayotte