Azuro (uk) Limited

Stephen Paul Wilcox

Paul Alexander Cunningham

Simon Kinahan

Ronald Ian Shipman

A method for estimating the average-case activity in a digital circuit includes the steps of identifying one or more predesignated types of circuit elements in the digital circuit, and propagating activity values through any identified circuit elements using a predetermined formula.

Estimation of average-case activity for circuit elements in a digital circuit

The present invention provides a method for estimating the average-case activity in a digital circuit. The method includes the steps of assigning initial activity values to outputs of flops in the digital circuit, and repeatedly updating the activity values in an iterative procedure until a predetermined termination criterion is met. The updating of the activity values uses a combination of standard probability updating techniques and predetermined formulae for obtaining the activity values of predesignated types of circuit elements in the digital circuit. The predesignated types of circuit elements include, for example, one or more of a clock-gated flop, an enable flop and a flop with a recirculation multiplexer.

Estimation of average-case activity for digital circuits

A method for estimating the average-case activity in a digital circuit includes the steps of identifying a state machine in the digital circuit, and propagating activity values through the state machine to obtain activity information at an output of a flop in the state machine using a predetermined formula.

Estimation of average-case activity for digital state machines

There is disclosed a method, and corresponding apparatus, for determining a clock gating function for a set of clocked state-holding elements, comprising the steps of: for each element, determining the conditions under which the element will hold its current value based only on those inputs which are common to all elements; and combining the conditions to form a gating function.

Generation of clock gating function for synchronous circuit

A method of determining a forced gating function for at least one of a plurality of clocked state-holding elements. The forced gating function compares the input and output of said at least one clocked state-holding element. The method simulates the performance of the element for different implementation conditions; measures the performance of the element for each condition, and determines the implementation of the forced gating function using the measured performances.

Clocked gating based on measured performance

There is disclosed a clock gating structure for a synchronous circuit comprising a plurality of clocked state holding elements, the clocked gating structure including at least one full-cycle clock gating cell and at least one half-cycle clock gating cell, and a method for designing and controlling such.

Clock gating for synchronous circuits

A method of transforming a first integrated circuit design comprising a plurality of D-type flip-flops each having a clock signal and being associated with an enable signal into a second integrated circuit design using guard-flops, the method comprising: identifying D-type flip-flops in the first integrated circuit design, and transforming each of the identified D-type flip-flops into a guard-flop comprising a transparent catch latch and a transparent pass latch; generating a catch enable signal for controlling the transparent catch latch from the clock signal and enable signal of the D-type flip-flop in the first integrated circuit design; and generating a pass enable signal for controlling the transparent pass latch based on the catch signals of at least some of the guard-flops that take data from the D-type flip-flop in the first integrated circuit design.

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Cambridge, United Kingdom

Stephen Paul Wilcox