Gennum Corporation

745 LLC

First Act Inc.

Stephen Paul Webster

Craig A Small

Mark S Izen

Bernard Chiu

Wendy Mittelstadt

Eliyahu D Zamir

Gabriel Viani

John Hudson

Jack Daniel Davis

Aapoolcoyuz Biman

Andrea Gaiter

David Yiu

Ilissa Schild

Paul Franzosa

Paul Fransoza

Birubi Ram Biman

Ilissa Brooke Schild

A fret and method of making the fret are disclosed. The fret can include a body portion made of a non-conductive material, a first end, a second end, and a length defined between the first and second ends. A plurality of electrically conductive elements can be disposed along at least part of the body portion. Each element can be electrically insulated from the other conductive elements by the body portion. The method can include 1) providing a blank formed of electrically conductive material, 2) processing the blank to provide a plurality of electrically conductive elements, 3) affixing a body portion made of a non-conductive material to the plurality of electrically conductive elements, the body portion electrically insulating each element from the other conductive elements, and 4) removing material from the processed blank and affixed body portion to form a perimeter of the fret in a desired shape.

Fret and method of manufacturing frets for stringed controllers and instruments

Mobile device holder

Stringed instruments, game controllers, and related structures and methods are described. A game controller having one or more strings is described for a computer gaming application. A plurality of frets can be disposed on a fingerboard and underlying the strings. The frets may include electrically conductive zones that can be electrically insulated from each other, and each zone corresponds to a different string. A polyphonic pickup having a plurality of wire-wound coils coupled to corresponding magnetic returns can be included, and can be adapted to detect striking of at least one of the strings by a user of the game controller. Output signals may be sent from the controller to the gaming application indicative of fingering of the game controller and the time at which the strings of the game controller are struck. Multi-mode apparatus are also described. A stringed apparatus may be used as both a game controller and an instrument.

Methods and apparatus for stringed controllers and instruments

Stringed instruments, game controllers, and related structures and methods are described. A game controller having one or more strings is described for a computer gaming application. Output signals may be sent from the controller to the gaming application indicative of fingering of the game controller and the time at which the strings of the game controller are struck. Multi-mode apparatus are also described. A stringed apparatus may be used as both a game controller and an instrument. Bracing structures and methods are also described for bracing stringed apparatus, such as stringed game controllers and instruments.

Methods and apparatus for stringed controllers and/or instruments

Electronic game components are described. The electronic game components may define radiation striking zones in which user strikes may be detected. In response to detecting the strikes, control signals for an audio generator or gaming console may be generated. The electronic game components may be used to simulate percussive instruments, with the radiation striking zones corresponding to percussive components of the simulated percussive instrument.

Methods and apparatus for input devices for instruments and/or game controllers

A digital communication system for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line comprises an open-loop equalizer circuit and a DDC extension circuit. The open-loop equalizer circuit is operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals. The DDC extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and clamp the receive end of the transmission line during a negative transition of the DDC communication signal.

System and method for processing digital visual interface communication data signals and display data channel communication signals over a transmission line

An extender circuit for handling a communication signal transmitted over a transmission line includes a voltage clamp and a current booster circuit. The voltage clamp is connected to a receive end of the transmission line and is operable to clamp a reflection signal caused by the communication signal received at the receive end of the transmission line. The current booster circuit is connected to the receive end of the transmission line and is operable to provide a boost current at the receive end of the transmission line during a positive transition of the communication signal.

Digital communication extender system and method

A digital communication system for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line comprises an open-loop equalizer circuit and a DDC extension circuit. The open-loop equalizer circuit is operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals. The DDC  extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and clamp the receive end of the transmission line during a negative transition of the DDC communication signal.

An equalizer circuit for equalizing first and second differential input signals comprises a differential pair, a reactive load, and first and second input followers. The differential pair defines first and second input nodes and first and second output nodes, and the reactive load is coupled to the differential pair. The first input follower circuit is connected to the first input node of the differential pair and is operable to receive the first differential input signal and to receive a first feedback signal from the differential pair and in response to generate a first input signal at the first input node of the differential pair. The second input follower circuit is connected to the second input node of the differential pair and is operable to receive the second differential input signal and to receive a second feedback signal from the differential pair and in response to generate a second input signal at the second input node of the differential pair.

Input follower system and method

A serial digital data communications receiver with an improved automatic cable equalizer that is less susceptible to jitter and has greater multi-standards capability, and an improved automatic gain control system with a DC restorer that provides optimal edge jitter performance while avoiding the possibility of a latch-up condition at the start of data transmission. The automatic cable equalizer for equalizing signals received over cables of different lengths has multiple stages each having a transfer function of 1&plus;Ki&lsqb;fi(j&ohgr;)&rsqb; wherein each of the Ki vary in accordance with a sequential gain control methodology. The AGC system uses the difference between band-pass filtered versions of the amplitudes of the input and output of a DC restorer based on quantized feedback, to regulate the AGC circuit. The DC restorer comprises a comparator for generating a quantized output and further clamps the input with a clamping circuit so that a version of the quantized output is fed back to the input while avoiding the possibility of operational failure of the comparator at the onset of data transmission.

Serial digital data communications receiver with improved automatic cable equalizer, AGC system, and DC restorer

A device for restoring DC and non-zero average components of a serially transmitted binary signal which has been AC coupled. The device comprises an input port for the binary signal, a clamping circuit, a feedback network, a summing node, and an output port. The input port includes a capacitor for coupling the binary signal to the summing node and the clamping circuit. The feedback network includes an input and an output which are also connected to the summing node. The clamping circuit clamps the positive and negative peaks of the AC coupled binary signal which exceed a predetermined range. The feedback network latches the AC coupled binary signal and produces a current signal. For a binary signal which is within the predetermined range, the clamping circuit exhibits a very high input impedance, thereby causing the current signal to charge the coupling capacitor and produce a voltage which is added to the AC coupled binary signal at the summing node. The output port includes a comparator which converts the restored AC coupled binary signal to digital logic levels. In another embodiment, the clamping circuit includes a current sensor for producing an amplitude signal which is indicative of the amplitude of the AC coupled binary signal. The amplitude signal is fed to an automatic gain controller which produces a gain control voltage for controlling the operation of a high frequency equalizer.

System for DC restoration of serially transmitted binary signals

An improved differential gain stage for a bipolar monolithic integrated circuit. The integrated circuit is formed from a semiconductor substrate, and the differential gain stage includes first and second bipolar transistors. The base of the first transistor and the base of the second transistor form a differential input for the gain stage comprising non-inverting and inverting inputs respectively. The collectors of the transistors form a differential output. The differential gain stage includes a capacitor stage comprising: a peaking capacitor, and first, second, third and fourth capacitor structures. The peaking capacitor is coupled between the emitters of the first and second transistors. The first and second capacitor structures are located at a first spaced relationship from the substrate and the first capacitor is coupled to the emitter of the first transistor and the second capacitor is coupled to the emitter of the second transistor. The third and fourth capacitor structures are located at a second spaced relationship from the substrate. The third capacitor is connected to the first capacitor and the connection forms a first node. The fourth capacitor is connected to the second capacitor and the connection forms a second node. The differential gain stage also includes first and second buffers. The first buffer has an input connected to the non-inverting input of the gain stage and an output connected to the first node. The second buffer has an input connected to the inverting input of the gain stage and an output connected to the second node.

Differential gain stage for use in a standard bipolar ECL process

A device for converting binary logic pulses into an output current and the output current being switchable between a positive and negative polarity. The device provides a charge pump circuit which is suitable for the phase-detector stage in a phase-locked loop (PLL) circuit. The charge pump circuit comprises an input stage for the 'UP' binary logic pulses and a second stage for the 'DOWN' binary logic pulses. The input stages comprise emitted-coupled transistor pairs. The circuit includes current sources and current sinks for generating the output current in the input stages in response to the binary logic pulses. The circuit features a pair of switch diodes coupled between the outputs of the input stages. The diodes form a commutator which controls the direction of the output current and the leakage current during the idle states. The circuit also includes a clamping circuit to limit the voltage swing across the switching diodes. The charge pump circuit according to the present invention exhibits a fast response time, a symmetrical response to the binary logic pulses, and virtually zero leakage current in the idle state. The charge pump circuit utilizes non-complimentary bipolar processes and is suitable for a monolithic integrated circuit implementation.

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Oakville, Canada

Stephen Paul Webster