Quickturn Design Systems, Inc.

Altera Corporation

Other

Quickturn Systems, Incorporated

Drc Computer Corporation

Security First Corporation

Monterey Design Systems, Inc.

Quickturn Design

Stephen Paul Sample

Michael R Butts

Rakesh H Patel

Kevin A Norman

Thomas S Payne

Michael R D'Amour

Mikhail Bershteyn

Chao Chiang Chen

Steven Mark Casselman

Babu Rao Kandimalla

Michael H Wang

Lawrence A Laurich

Jerry R Bauer

Rick L Orsini

Mark S O'Hare

Don Martin

Terry L Goode

Jonathan Frankle

Wei-Jin Dai

Barton Quayle

Ara Markosian

Dam Van Bui

Yaacov I Greidinger

David S Reed

Hasmik Lazaryan

Louis Galbiati, Iii

Joseph Varghese

Data processing and an accelerator system therefor are described. An embodiment relates generally to a data processing system. In such an embodiment, a bus and an accelerator are coupled to one another. The accelerator has an application function block. The application function block is to process data to provide processed data to storage. A network interface is coupled to obtain the processed data from the storage for transmission.

Accelerator system for remote data storage

Data processing and an accelerator system therefore are described. An embodiment relates generally to a data processing system. In such an embodiment, a bus and an accelerator are coupled to one another. The accelerator has an application function block. The application function block is to process data to provide processed data to storage. A network interface is coupled to obtain the processed data from the storage for transmission.

Accelerator system for use with secure data storage

A configurable processor module accelerator using a programmable logic device is described. According to one embodiment, the accelerator module includes a circuit board having coupled thereto a first programmable logic device, a controller, and a first memory. The first programmable logic device has access to a bitstream which is stored in the first memory. Access to the bitstream by the first programmable logic device is controlled by the controller. The bitstream is capable of being instantiated in the first programmable logic device using programmable logic thereof to provide at least a transport interface for communication between the first programmable logic device and one or more other devices associated with the motherboard using the microprocessor interface.

Configurable processor module accelerator using a programmable logic device

A hardware emulation system is disclosed which reduces hardware cost by time multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The hardware emulation system comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces through the use of multiplexing.

Emulation system with time-multiplexed interconnect

A programmable logic device architecture. This programmable logic architecture includes a first logic block () containing programmable logic elements for performing logic functions. The architecture may also include a diagnostic block interface (), which interfaces with the first logic block (), for performing JTAG functions, configuring the first logic block (), initializing the first logic block (), interfacing with off-chip diagnostic and test devices and equipment, and performing other similar functions. The first logic block () may be programmably coupled to other components on the integrated circuit using a first programmable interconnect network (). The first logic block () includes a plurality of second logic blocks () which may be programmably coupled using a second programmable interconnect network (). The second programmable interconnect network () may be programmably coupled to the first programmable interconnect network (). Furthermore, the plurality of second logic blocks () include a plurality of third logic blocks () which may be programmably coupled using a third programmable interconnect network (). A signal from a third logic block () may be programmably coupled to the other logic blocks, the diagnostic block interface (), and other circuitry on the integrated circuit. The internal circuitry of these logic blocks may be monitored through a variety of programmable interconnect paths. This architecture is useful when debugging a design, especially for emulation and prototyping applications.

High-performance programmable logic architecture

A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system a network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

Apparatus for emulation of electronic systems

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Memory circuit for use in hardware emulation system

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common input/output pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system. A method for dynamically testing the interconnect between integrated circuits is also disclosed.

Method and apparatus for dynamically testing electrical interconnect

A logic chip useful for emulation and prototyping of integrated circuits. The logic chip comprises a plurality of logic elements, which is divided into a plurality of subsets of logic elements. The logic chip further comprises a plurality of first level interconnects. The plurality of first level interconnects interconnect one of the plurality of subsets of logic elements, thereby forming a plurality of first level logical units. The plurality of first level logical units is divided into a plurality of subsets of first level logical units. The logic chip also comprises a plurality of second level interconnects. The second level interconnects interconnect one of the plurality of subsets of first level logic units, thereby forming a plurality of second level logic units. The logic chip also comprises a third level interconnect. The third level interconnect interconnects the plurality of second level logic units, thereby forming a third level logic.

Optimized emulation and prototyping architecture

A programmable logic device architecture. This programmable logic architecture includes a first logic block ( ) containing programmable logic elements for performing logic functions. The architecture may also include a diagnostic block interface ( ), which interfaces with the first logic block ( ), for performing JTAG functions, configuring the first logic block ( ), initializing the first logic block ( ), interfacing with off-chip diagnostic and test devices and equipment, and performing other similar functions. The first logic block ( ) may be programmably coupled to other components on the integrated circuit using a first programmable interconnect network ( ). The first logic block ( ) includes a plurality of second logic blocks ( ) which may be programmably coupled using a second programmable interconnect network ( ). The second programmable interconnect network ( ) may be programmably coupled to the first programmable interconnect network ( ). Furthermore, the plurality of second logic blocks ( ) include a plurality of third logic blocks ( ) which may be programmably coupled using a third programmable interconnect network ( ). A signal from a third logic block ( ) may be programmably coupled to the other logic blocks, the diagnostic block interface ( ), and other circuitry on the integrated circuit. The internal circuitry of these logic blocks may be monitored through a variety of programmable interconnect paths. This architecture is useful when debugging a design, especially for emulation and prototyping applications.

An automated method of designing large digital integrated circuits using a software program to partition the design into physically realizable blocks and then create the connections between blocks so as to maximize operating speed and routability while minimizing the area of the resulting integrated circuit. Timing and physical constraints are generated for each physically realizable block so that standard-cell place and route software can create each block independently as if it were a separate integrated circuit.

Method for designing large standard-cell base integrated circuits

A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system. A network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

Apparatus for emulation of electronic hardware system

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Growing community of inventors

Saratoga, CA, United States of America

Stephen Paul Sample