Xockets, Inc.

Cisco Technology, Inc.

Other

Stephen Paul Belair

Parin Bhadrik Dalal

David Delano Ward

Sudhakar Mamillapalli

Pradeep Kumar Kathail

Michael Brian Galles

Kenneth A Moberg

Daljeet Singh

Ronnie B Kon

Matthew F Williams

Arthur B Stine

Venkatasiva Mortala

Shawn Morrissey

Satisha Bhat

Matthew Williams

A network overlay system can include a data transport module having a network interface and a translation module configured to generate offload processing addresses for the network packet data; a system bus; at least one host processor connected to the system bus; and at least one offload processor module coupled to the system bus and configured to receive network packet data associated. Offload processor modules include processing circuits associated with at least one of the offload processing addresses that are configured to encapsulate the network packet data for transport on a logical network or decapsulate the network packet data received from the logical network. The offload processing circuits encapsulate or decapsulate network packet data independent of any host processor.

Network overlay systems and methods using offload processors

A distributed computing architecture for executing at least first and second computing operations executed in parallel on a set of data, can include a plurality of servers, including first servers that each include at least one central processing unit (CPU), and at least one offload processing module coupled to CPU by a bus. Each offload processing module can include computation elements. The computation elements can be configured to operate as a virtual switch, and to execute the second computing operations on first processed data to generate second processed data. The virtual switches can form a switch fabric for exchanging data between the offload processing modules. The second computing operations are executed on a plurality of the offload processing modules in parallel.

Architectures and methods for processing data in parallel using offload processing modules insertable into servers

A structured data processing system is disclosed that can include a plurality of XIMM modules connected to a memory bus in a first server, with the XIMM modules each respectively having a DMA slave module connected to the memory bus and an arbiter for scheduling tasks, with the XIMM modules providing an in-memory database; and a central processing unit (CPU) in the first server connected to the XIMM modules by the memory bus, with the CPU arranged to process and direct structured queries to the plurality of XIMM modules.

Processing structured and unstructured data using offload processors

A distributed system server system for providing network overlay services is disclosed. The system can include at least two servers; and a plurality of offload processor modules, each having an input-output (IO) port and multiple offload processors, and including at least a first offload processor module configured to receive and process network packets having a logical identifier, and a second offload processor connected directly to the first offload processor through their respective IO ports, and configured to process at least a portion of the packets having the logical identifier, and returning the processed packets through its IO port.

Full bandwidth packet handling with server systems including offload processors

An inter-rack server system for a packet processing is disclosed. The system can include a plurality of servers arranged into multiple racks a plurality of top of rack (TOR) units connected to the servers, each TOR unit configured to operate as a TOR switch connecting each of the racks to another of the racks, and a plurality of offload processor modules, each offload processor module having an input-output (IO) port and multiple offload processors, wherein a first offload processor module on a first server on a first rack is connected directly to a second offload processor module on a second server on a second rack, with connection provided through respective IO ports.

A distributed system server system for a packet processing without top of rack (TOR) units is disclosed. The system can include a plurality of servers, each having at least one host processor, and a plurality of offload processor modules, each offload processor module having an input-output (IO) port and multiple offload processors, wherein a first offload processor module is connected directly to a second offload processor module through respective IO ports, the first and second offload processors configured to provide bidirectional network packet flow between at least the first and second offload processor modules and at least one host processor without TOR units for an inter-server connection.

A rack server system for a map/reduce data processing is disclosed. The method can include a plurality of servers arranged in a rack, and a plurality of offload processor modules supported on at least two of the servers, each offload processor module having an input-output (IO) port and multiple offload processors, a first offload processor module configured to execute map steps of the map/reduce data processing, and being connected directly to a second offload processor through their respective IO ports to define a midplane switch, wherein the second offload processor module is configured to execute reduce steps of on data provided from the first offload processor module.

A rack server system for a packet processing is disclosed. The system can include a plurality of servers mountable in a rack; a top of rack (TOR) unit having connections to each of the servers; and a plurality of offload processor modules, each offload processor module having at least one input-output (IO) port and multiple offload processors, including at least a first offload processor module connected directly to a second offload processor module through their respective IO ports.

A system can include a host processor connected to memory via a system memory bus; and at least one offload processor module, including at least one offload processor mounted on the offload processor module, and configured to execute operations on data received over the system memory bus, and to output context data to memory, and read context data from the memory, and hardware scheduling logic mounted on the module and configured to control operations of the at least one offload processor.

Offload processor modules for connection to system memory, and corresponding methods and systems

A packet handling system is disclosed that can include at least one main processor, a plurality of offload processors connected to a memory bus and configured to provide security related services on packets prior to redirection to the main processor; an arbiter connected to each of the plurality of offload processors, the arbiter capable of scheduling resource priority for instructions or data received from the memory bus; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus, and further directing at least some memory read/write data to the arbiter.

Efficient packet handling, redirection, and inspection using offload processors

A method for providing network overlay services using a distributed system server system is disclosed. The method can include providing at least two servers, providing bidirectional network packet flow through input-output (IO) ports of at least two offload processor modules, providing a direct connection between the IO ports of the at least two offload processor modules, and processing network packet data corresponding to a bidirectional network packet flow and a logical identifier with at least one of the offload processor modules.

A system can include at least one offload processor having a data cache, the offload processor including a slave interface configured to receive write data and provide read data over a memory bus; an offload processor module including context memory and a bus controller connected to the slave interface; and logic coupled to the offload processor and context memory and configured to detect predetermined write operations over the memory bus; wherein the offload processor is configured to execute operations on data received over the memory bus, and to output context data to the context memory, and read context data from the context memory.

Disclosed are various ways of performing reliable multicast communication which may include, for example, designating which node or nodes to acknowledge a message and/or whether to immediately acknowledge or delay acknowledgement of a message, which may be of particular use with routers, packet switching systems, computer systems, and other devices. Multiple nodes are typically sent a multicast message, which includes an indication of one or more designated nodes to acknowledge the message, a sequence number or other message identification value, and possibly an indication whether an immediate or delayed acknowledgment is requested. A node receiving the message responds accordingly if it is designated to acknowledge the message, which may include requesting any missing messages, and/or sending an acknowledgment message for the messages it has received since it sent its last acknowledgment message.

Reliable multicast communication

Disclosed are mechanisms for initiating and performing tasks by a gang of members. A member of a gang identifies an event or other condition which requires notification to and/or action to be taken by at least a subset, if not all the other members of the gang. The gang member notifies other gang members by sending a message, such as that using reliable group communication using multicast and/or unicast messages. The information notified to other gang members and/or actions to be performed are extensible to meet the needs of the wide-variety of possible applications. A small list of example subject areas of these applications includes collecting, distributing, updating, responding to, and/or other processing of error conditions, routing information (e.g., between systems, from a route processor to line cards within a system, etc.), configuration information, flow control information, statistics or other values, etc.

Gang scheduling among one or more components or systems

A lightweight messaging method and apparatus that includes creating a temporary receive data area, and if a receive operation is seen first, then creating an operational receive data area, and waiting for a corresponding send operation to fill the operational receive data area with sent data; and if the send operation is seen first, then filling the temporary receive data area with sent data, when the corresponding receive operation is seen, creating the operational receive data area, and moving the sent data from the temporary receive data area to the operational receive data area.

Growing community of inventors

Santa Cruz, CA, United States of America

Stephen Paul Belair